Re: code optimization in VHDL compilers ?

"Rainer Leupers" <leupers@iss.rwth-aachen.de>
3 Feb 2005 22:44:23 -0500

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Related articles
code optimization in VHDL compilers ? srikanth.kamath@gmail.com (2005-01-24)
Re: code optimization in VHDL compilers ? leupers@iss.rwth-aachen.de (Rainer Leupers) (2005-02-03)
Re: code optimization in VHDL compilers ? ramesh@tharas.com (2005-02-03)
Re: code optimization in VHDL compilers ? srikanth.kamath@gmail.com (Srikanth) (2005-02-06)
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From: "Rainer Leupers" <leupers@iss.rwth-aachen.de>
Newsgroups: comp.compilers
Date: 3 Feb 2005 22:44:23 -0500
Organization: Compilers Central
References: 05-01-078
Keywords: code, optimize
Posted-Date: 03 Feb 2005 22:44:23 EST

The LANCE compiler translates ANSI C source code to
ANSI C three address code. You can download the frontend from:


http://www.icd.de/es/lance/lance.html


Of course, for VHDL a different tool would be required.
However, you may use the LANCE frontend to study the three address
code templates used for a translating a behavioral description
with high-level language constructs (control flow, composite
data type access, etc.) into three address code.


"Srikanth Kamath" <srikanth.kamath@gmail.com> schrieb
> I'm working on Code optimizer for VHDL.I will be using 3 address code
> as input to my optimizer program .Could you please suggest ways to
> generate 3 address Code from a behavioural description ?
> If you have worked on this /related area, please suggest useful
> material /links

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