Re: Register allocation

gopi@sankhya.com (Gopi Bulusu) wrote in message news:04-07-074...
> > I am trying to get the performance estimates of a C program. But at
> > the moment I am ignoring the act that the number of registers are
> > limited. I am assuming that the processor has infinite registers. What
> > I would like to know is what range of error I might run into under
> > such assumption.
>
> Let's assume that the processor has only 1-register. Then every use of
> a virtual register in your "infinite register set" will need spill
> code to be generated which is an overhead of approximately 1-store and
> 1-load for every register access. That's the theoretical worst case
> (actual can be worse. I spent a total of only 30-seconds on this one,
> so any corrections are welcome :-)
>


The overhead is 1-load and 1-store, but the overhead isn't as high as
you would expect, thanks to a hierarchy of caches to speed things up.
No doubt the speed with which a register can be accessed is much
higher than a first-level cache access, but the performance difference
between a good and bad allocation strategy may not amount to a lot
[and that is a guess].


regards
-kamal

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