Re: Register allocation

gopi@sankhya.com (Gopi Bulusu)
28 Jul 2004 12:07:58 -0400

          From comp.compilers
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From: gopi@sankhya.com (Gopi Bulusu)
Newsgroups: comp.compilers
Date: 28 Jul 2004 12:07:58 -0400
Organization: http://groups.google.com
References: 04-07-044
Keywords: registers
Posted-Date: 28 Jul 2004 12:07:58 EDT

> I am trying to get the performance estimates of a C program. But at
> the moment I am ignoring the act that the number of registers are
> limited. I am assuming that the processor has infinite registers. What
> I would like to know is what range of error I might run into under
> such assumption.


Let's assume that the processor has only 1-register. Then every use of
a virtual register in your "infinite register set" will need spill
code to be generated which is an overhead of approximately 1-store and
1-load for every register access. That's the theoretical worst case
(actual can be worse. I spent a total of only 30-seconds on this one,
so any corrections are welcome :-)


Btw, among the popular compilers, gcc is an example of a compiler that
makes such an assumption. The reload phase of gcc essentially takes
care of mapping a theoretical infinite register set to the actual
finite register set of a particular processor.


Unless you are dealing with a trivial C program, number of registers
is probably not the most important thing that impacts the error range
of your estimate, a good optimizer (which will include a good global
register allocator) will probably impact it a lot more.


Regards,
gopi


---


Gopi Kumar Bulusu
Sankhya Technologies Private Limited
http://www.sankhya.com
Tel: +91 891 554 2666
Fax: +91 891 554 2665

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