Re: Precedence based parsing

    Our open source Verilog simulator uses operator precedence to parse
Verilog expressions as a separate section of a hand coded recursive
descent parser. The operator precedence code uses procedure calls
following algorithm in Gries' old compiler book (Gries, D. "Compiler
construction for digital computers").


    GPL Cver home page is www.pragmatic-c.com/gpl-cver. You can see the code
in the v_src2.c file.


    Verilog expressions are complex and language is irregular and non context
free. For example, scanner requires information from state of parser to
distinguish tokens. Such language constructs are what hardware designers
want.


    In a more general sense, I have never understood why people insist
on using weak push down autamata (PDA) machine parsing tables when
programming languages provide the full power of Turing Machines.
/Steve


On 20 Dec 2003 11:49:33 -0500, Clint Olsen <clint@0lsen.net> wrote:
> On 2003-12-14, Rob Thorpe <robert.thorpe@antenova.com> wrote:
>
>> Especially where the larger parser was top-down. This was done to
>> make the parser faster, but today a top-down parser is normally fast
>> enough anyway when you can use one.
>
> Perhaps I'm missing something obvious, but you can do efficient
> precedence-based top-down parsing, so I don't quite know what's so
> great about this method. Using a precedence table, you can decide
> whether or not a recursive call is necessary to parse a higher
> precedence operator. Hanson and Fraser cover this in their book, "A
> Retargetable C Compiler : Design and Implementation."
>
> -Clint
> [It probably made more difference when the whole compiler had to fit
> into 24K bytes. -John]


--
Steve Meyer Phone: (612) 371-2023
Pragmatic C Software Corp. email: sjmeyer@pragmatic-c.com
520 Marquette Ave. So., Suite 900
Minneapolis, MN 55402

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