Re: Retargetable Compiler Environment for DSPs?

Ian L. Kaplan wrote:


> Oliver Wahlen <oliver.wahlen@post.rwth-aachen.de> wrote:
>>What is still
>>missing is a way to generate a compiler or at least compiler
>>components for DSPs.
>
> Compilers that optimizes for VLIW, software pipelining and SIMD will
> probably have different high level optimization phases. For
> example, SIMD and VLIW compilers use a technique for "strip mining"
> loops to target the multiple functional units. This is usually done
> in the IR, rather than at the code generation stage. Software
> pipelining requires a different IR optimization phase.


The funny thing is that for example the c6x family of Texas Instuments
is somehow a VLIW architectur, has SIMD instruction _and_ is made for
software pipelining. (Actually they do not call it VLIW. I think the
name is "static superscalar" but this simply is an improvement of
VLIW).


It seems that for all combination of architectural "tricks" you find a
DSP :-)


This is why I find your idea of a modular compiler for all "flavours"
of DSPs very interesting. The question is if one can find an IR or
lets better say a set of IR-Levels (HIR,MIR,LIR) that is powerfull
enough to address all DSP architectural features that are currently
available. I am interested in your opinion if this is a critical
issue or if the problem would "only" be to program all the
optimization and code generation modules and some sort of controller
for their interaction.


> I believe that the way to target multiple DSP architectures is to
> build a modular compiler. This compiler would allow optimization
> components to be plugged in for different architectures. But each
> component would have to be crafted for the particular architecture.


In how far do you think that "crafted" means writing compiler
components by hand: You can write a pattern matcher completely by hand
but you can also generate one based on a pattern matcher description
(which you wrote by hand).
--
Greetings,
Oliver Wahlen

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