Related articles |
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Retargetable Compiler Environment for DSPs? oliver.wahlen@post.rwth-aachen.de (Oliver Wahlen) (2001-01-09) |
Re: Retargetable Compiler Environment for DSPs? nr@labrador.eecs.harvard.edu (2001-01-11) |
Re: Retargetable Compiler Environment for DSPs? iank@idiom.com (2001-01-11) |
Re: Retargetable Compiler Environment for DSPs? oliver.wahlen@post.rwth-aachen.de (Oliver Wahlen) (2001-01-20) |
Re: Retargetable Compiler Environment for DSPs? oliver.wahlen@post.rwth-aachen.de (Oliver Wahlen) (2001-01-20) |
Re: Retargetable Compiler Environment for DSPs? iank@idiom.com (2001-01-26) |
From: | iank@idiom.com (Ian L. Kaplan) |
Newsgroups: | comp.compilers |
Date: | 11 Jan 2001 12:30:12 -0500 |
Organization: | Unknown |
References: | 01-01-031 |
Keywords: | DSP |
Posted-Date: | 11 Jan 2001 12:30:12 EST |
Oliver Wahlen <oliver.wahlen@post.rwth-aachen.de> wrote:
>What is still
>missing is a way to generate a compiler or at least compiler
>components for DSPs.
Compilers that optimizes for VLIW, software pipelining and SIMD will
probably have different high level optimization phases. For
example, SIMD and VLIW compilers use a technique for "strip mining"
loops to target the multiple functional units. This is usually done
in the IR, rather than at the code generation stage. Software
pipelining requires a different IR optimization phase. In the same
way, conditional execution (a la IA64) requires special
optimizations that may be reflected in the intermediate.
I believe that the way to target multiple DSP architectures is to
build a modular compiler. This compiler would allow optimization
components to be plugged in for different architectures. But each
component would have to be crafted for the particular architecture.
Ian Kaplan
iank@bearcave.com
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