Return to the
comp.compilers page.
Search the
comp.compilers archives again.
| Related articles |
|---|
| Testing the performance of Instruction Scheduler. phani.sesha@wipro.com (phani narasimhan venkata sesha myreddy) (2000-11-09) |
| Re: Testing the performance of Instruction Scheduler. gporr@gscdump.columbiasc.ncr.com (2000-11-09) |
| Re: Testing the performance of Instruction Scheduler. d97roli@dtek.chalmers.se (2000-11-11) |
| Re: Testing the performance of Instruction Scheduler. Sid-Ahmed-Ali.TOUATI@inria.fr (Sid Ahmed Ali TOUATI) (2000-11-11) |
| Re: Testing the performance of Instruction Scheduler. plakal@nospam-cs.wisc.edu (2000-11-16) |
| From: | gporr@gscdump.columbiasc.ncr.com (Greg Porr) |
| Newsgroups: | comp.compilers |
| Date: | 9 Nov 2000 16:51:43 -0500 |
| Organization: | NCR Corp., Columbia SC |
| References: | 00-11-067 |
| Keywords: | architecture, optimize |
| Posted-Date: | 09 Nov 2000 16:51:43 EST |
I don't know about the ultrasparc, but tools like "emon" on Intel x86
provide exactly that kind of information. It's a matter of enabling
certain performance monitoring counters within the cpu itself. As emon
was originally (and perhaps still is) supplied directly by Intel, perhaps
Sun has similar tools for their processors.
- Greg
"phani narasimhan venkata sesha myreddy" <phani.sesha@wipro.com> writes:
>hai all,
>How much performance gain can be expected from an instruction scheduler?
Return to the
comp.compilers page.
Search the
comp.compilers archives again.