Re: Using C as a back end

On 23 Oct 2000 21:59:42 -0400, sjmeyer@www.tdl.com (Steve Meyer)
wrote:


>But it turns out most statements in Verilog are independent so
>optimizer does not really need to look for basic blocks across Verilog
>statement boundaries. Is there a way to tell C compiler optimizer
>about this property? I have tried surrouding C statements with extra
>level block ({}) with no declarations but it does ont seem to help.
>Breaking long sections into multiple procedures seems to be even worse
>because there are many context C variables needed in Verilog execution
>so procudural call over head slows down exection speed.


Curly braces are only scoping clues. Blocks end whenever there is a
branch in the code - you might try tricking the compiler by something
like the following:


A: <code for verilog statement>
        goto B;
B: <code for verilog statement>
        goto C:
C: ...


It looks stupid, but the compiler might take the hint. Hopefully the
useless jumps would be eliminated by the optimizer.




Another way would be to bundle all the state variables into a
structure and generate a separate, one parameter function for each
verilog statement which explicitly tail calls the next function. Also
sounds stupid, but GCC will *sometimes* understand this and optimize
the function calls away.


Your mileage may vary.


George Neuner
Dynamic Resolutions, Inc.

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