Re: Compiler for VLIW Architecture

Gerd Bleher <gerdb@bstde006.bbn.hp.com>
14 Apr 2000 23:50:34 -0400

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From: Gerd Bleher <gerdb@bstde006.bbn.hp.com>
Newsgroups: comp.compilers
Date: 14 Apr 2000 23:50:34 -0400
Organization: Agilent Technologies Deutschland GmbH, SSTD R&D
References: 00-04-016 00-04-080
Keywords: architecture, performance, comment

> First, HP has had a VLIW RISC device out for a while, PA-RISC, I
> think..


Not really, even though an instructions like
shift-,-add-and-conditionally-nullify-next-instruction might have the
air of VLIW at a first glance ;-)


An interesting approach of optimizing for VLIW architectures is
described in http://www.research.ibm.com/vliw/ however I'm not aware
of its practical relevance.


Gerd
--
Gerd Bleher; Agilent Technologies GmbH; Silicon-Systems Test Division;
Herrenberger Str. 130; 71034 Boeblingen; Germany
[Several of the Multiflow VLIW guys went to HP, but they didn't have
anything I know of to do with PA-RISC. -John]

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