Re: Compiler for VLIW Architecture (RKRayhawk)
11 Apr 2000 14:33:24 -0400

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From: (RKRayhawk)
Newsgroups: comp.compilers
Date: 11 Apr 2000 14:33:24 -0400
Organization: AOL
References: 00-04-016
Keywords: architecture

A few general leads may help ...

First, HP has had a VLIW RISC device out for a while, PA-RISC, I
think.. Following leads from there may get you to some literature
that discusses compilation, and performance optimization.

The joint effort by Intel and HP, producing the IA-64, also invovles a
VLIW machine, the instruction groups are VLIWs. Their sites may also
have material on compilers and scheduling issues per optimization.

In addition to being VLIW in character, Intel's IA-64 reveals a major
trend away from idealistic RISC design. The stack in IA-64 is strongly
indicative of accomplishments by Sun in execution time performance
boosting. To get that gain the code generator must cognize the
floating stack top.

You can project forward from IA-64 to any group or site that is
promising, say a linux, for the IA-64 and see if these sites have
available documentation or references to such publishings. There are
some pretty smart folks working on this sort of stuff, but the
commercial projects are likely currently preoccupied with just getting
validity, not optimization (but that is mere speculation).

I honestly believe you can get good leads if you agressively pursue
the webmasters at the HP and Intel sites.

Considering the locale of the vendors of the leading (see P.S. on
'leading' below) hardware, it is not unlikely that you could get
excellent leads to documentation and to experts if you search at the
sites of

Stanford University in Palo Alto, California.

If it would be useful to you for me to try to assist you to find other
specific URLs, please email me.

Second, less exact, most of the RISC machines involve superscalar
internals that lead to consideration of optimizing code generation in
terms of inter-dependencies in data flow and control flow. It is not
an exact response to your question, but the literature on optimized
parallel code execution, in general, relates to your interests in
performance techniques. Superscalars harnessed to intricate
dispatcher/completer devices are just VLIW machines with flexible
length instruction words.

VLIWs machines, for example, have available null subfields that allow
them to also vary instruction content, even if in a fixed width. That
is it took until the later part of the twentieth century for mankind
to be intelligent enough to re-invent the zero, which is what a null
slot is.

Thirdly, you indicated "Also I would be glad if you could provide me
with articles and journals in this topic as soon as possible." Well,
..., I am a novice I assure you, but you should ask for an extension
to whatever is driving you to a short deadline. The subject of
improving the performance of compilers for VLIW and related
architectures is large.

Indeed, anything that has a parallel execution of two or more
instructions is a VLIW in behavior, even if multiple instructions are
not accessed simulaneously. For example, the Advanced Micro Devices
Am29000 has a 'delayed' branch instruction. It takes a cycle or so to
do its thing. Meanwhile the _next_ instruction also executes! Takes
some planning to generate code for that properly, any literature that
generalizes about such scheduling relates to your interest. At a
tangent, no doubt, but I am just saying the isssue is large, and the
material to date is not necessarily organized under the title VLIW.

Since you post from Ra.MsState.Edu then maybe you want the latest,
greatest, and most likely to be widely distributed device, so go for
the IA-64 and see if you can find the literature that guided them to
predicates. Let me know if you would like assistance towards more
specific URLs.

P.S. To those familiar with other VLIWs that have actually hit the
pavement, the above post is not meant to diminish their significance,
nor express the likelihood that the best available docs are along the
HP/Intel path. Instead, the miopia is just clear representation of my
limited exposure, and I too would really like leads to other VLIW
architecture that has actually been wired.

Best Wishes,

Robert Rayhawk

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