Re: how do a RISC compiler translate an array initialization ?

Sid Ahmed Ali TOUATI <Sid-Ahmed-Ali.TOUATI@inria.fr>
7 Aug 1999 01:37:07 -0400

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how do a RISC compiler translate an array initialization ? Sid-Ahmed-Ali.TOUATI@inria.fr (Sid Ahmed Ali TOUATI) (1999-08-02)
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Re: how do a RISC compiler translate an array initialization ? pmichaud@irisa.fr (1999-08-04)
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Re: how do a RISC compiler translate an array initialization ? Sid-Ahmed-Ali.TOUATI@inria.fr (Sid Ahmed Ali TOUATI) (1999-08-07)
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From: Sid Ahmed Ali TOUATI <Sid-Ahmed-Ali.TOUATI@inria.fr>
Newsgroups: comp.compilers,comp.arch
Date: 7 Aug 1999 01:37:07 -0400
Organization: INRIA
References: 99-08-015 99-08-023
Keywords: architecture, performance

Pierre Michaud wrote:


> The Ultrasparc data cache is write-through.


hmmm...
Effectively, write-throught strategy means that when a cache line is
modified, the update is reported to the line directly in order to
garantee the data coherence between memory and caches. When a data is
not present in the cache, it is not loaded from main memory (no write
allocate), so it seems that it does not generate a
cache-write-miss. The ultra sparc contain a specific register to count
Dcache-write-reference (register PCR_S0_DC_WRITE) and a
Dcache-write-hit (register PCR_S1_DC_WRITE_HIT). I think that
cache-write-miss could be obtained indirectly by the formula:
cache-write-miss = cache-write-reference minus cache-write-hit




thanks


SAAT


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