Re: Register allocation and instruction scheduling

adrian@dcs.rhbnc.ac.uk (A Johnstone)
1 Feb 1999 23:36:02 -0500

          From comp.compilers

Related articles
[3 earlier articles]
Re: Register allocation and instruction scheduling bob.morgan@digital.com (1999-01-20)
Re: Register allocation and instruction scheduling greened@zip.eecs.umich.edu (David A. Greene) (1999-01-22)
Re: Register allocation and instruction scheduling bob.morgan@digital.com (1999-01-25)
Re: Register allocation and instruction scheduling mikesw@whiterose.net (1999-01-27)
Re: Register allocation and instruction scheduling zalman@netcom.com (1999-01-27)
Re: Register allocation and instruction scheduling anton@mips.complang.tuwien.ac.at (1999-01-31)
Re: Register allocation and instruction scheduling adrian@dcs.rhbnc.ac.uk (1999-02-01)
| List of all articles for this month |

From: adrian@dcs.rhbnc.ac.uk (A Johnstone)
Newsgroups: comp.compilers
Date: 1 Feb 1999 23:36:02 -0500
Organization: Royal Holloway, University of London
References: 99-01-055 99-01-076 99-01-077 99-01-092
Keywords: optimize, registers

On 22 Jan 1999 21:25:11 -0500, "David A. Greene" <greened@zip.eecs.umich.edu> wrote:
: >Aren't the limited capability of the execution units (if they are not
: >uniform) and number of cache ports (or degree of overlapping) usually
: >the main structural hazards? It seems a bit silly that a processor
: >would run out of physical registers. Now a clustered register file is
: >another issue entirely and there the compiler can help.


Bob Morgan (bob.morgan@digital.com) wrote:
: If we are trying to put resources on a chip there are always
: limitations. Furthermore the bigger the register file, the slower the
: access to registers and the more control structure controlling the
: registers.


I'm not quite sure I agree that the number of registers adversely
affects hardware speed. The main reason why most processors have
restricted numbers of registers is to keep down the number of bits
needed in the instruction word to specify them. A typical 32 register
RISC needs 15 bits to specify the registers taking part in a 3-address
instruction. 64 registers would need 18 bits, which then compromises
the designer's ability to specify all the needed functionality in a
32-bit instruction word. The best supporting example I can give you is
the SPARC architecture which gives the programmer lots (192?) general
purpose registers but uses a windowing scheme linked to the procedure
call mechanism to switch registers in and out of context. In this way,
only 32 registers are visible at any one time, keeping the instruction
word length manageable.


                                                      Adrian
--
Dr Adrian Johnstone, Senior Lecturer in Computing, Computer Science Dep,
Royal Holloway, University of London, Egham, Surrey, TW20 0EX, England.
Email a.johnstone@rhbnc.ac.uk Tel:+44(0)1784 443425 Fax:+44(0)1784 439786


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