Re: Register allocation and instruction scheduling

"David A. Greene" <greened@zip.eecs.umich.edu>
22 Jan 1999 21:25:11 -0500

          From comp.compilers
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Re: Register allocation and instruction scheduling greened@zip.eecs.umich.edu (David A. Greene) (1999-01-19)
Re: Register allocation and instruction scheduling bob.morgan@digital.com (1999-01-20)
Re: Register allocation and instruction scheduling greened@zip.eecs.umich.edu (David A. Greene) (1999-01-22)
Re: Register allocation and instruction scheduling bob.morgan@digital.com (1999-01-25)
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Re: Register allocation and instruction scheduling zalman@netcom.com (1999-01-27)
Re: Register allocation and instruction scheduling anton@mips.complang.tuwien.ac.at (1999-01-31)
Re: Register allocation and instruction scheduling adrian@dcs.rhbnc.ac.uk (1999-02-01)
| List of all articles for this month |
From: "David A. Greene" <greened@zip.eecs.umich.edu>
Newsgroups: comp.compilers
Date: 22 Jan 1999 21:25:11 -0500
Organization: Department of Electrical Engineering and Computer Science, The University of Michigan
References: 99-01-055 99-01-076
Keywords: architecture, optimize

Bob Morgan wrote:


> [ optimizing code when there's register renaming ]


Is this really a problem, though? I was under the impression that
a processor such as the PA 8K has a maximum number of in-flight
instructions and the hardware resources such as the instruction
buffer/reservation stations, execution units and physical registers
are all tailored to this number.


Aren't the limited capability of the execution units (if they are not
uniform) and number of cache ports (or degree of overlapping) usually
the main structural hazards? It seems a bit silly that a processor
would run out of physical registers. Now a clustered register file is
another issue entirely and there the compiler can help.


                                                                                        -Dave

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