|[2 earlier articles]|
|Re: How about VLIW used as RISC? firstname.lastname@example.org (Ricardo Bugalho) (2004-04-29)|
|Re: How about VLIW used as RISC? email@example.com (2004-04-29)|
|Re: How about VLIW used as RISC? MitchAlsup@aol.com (2004-04-29)|
|Re: How about VLIW used as RISC? firstname.lastname@example.org (Alex Colvin) (2004-05-02)|
|Re: How about VLIW used as RISC? email@example.com (glen herrmannsfeldt) (2004-05-02)|
|Re: How about VLIW used as RISC? firstname.lastname@example.org (Stan Lass) (2004-05-02)|
|Re: How about VLIW used as RISC? email@example.com (Sander Vesik) (2004-05-08)|
|Re: How about VLIW used as RISC? firstname.lastname@example.org (Ricardo Bugalho) (2004-05-08)|
|Re: How about VLIW used as RISC? email@example.com (glen herrmannsfeldt) (2004-05-09)|
|From:||Sander Vesik <firstname.lastname@example.org>|
|Date:||8 May 2004 21:07:32 -0400|
|Organization:||Ye 'Ol Disorganized NNTPCache groupie|
|References:||04-04-088 04-04-104 04-05-006|
|Posted-Date:||08 May 2004 21:07:32 EDT|
In comp.arch glen herrmannsfeldt <email@example.com> wrote:
> Ricardo Bugalho wrote:
> > On Wed, 28 Apr 2004 15:33:26 -0400, Ron wrote:
> >>So what is your opinion?
> > VLIW is only interesting if you want to build a one way (one instruction
> > word) in-order CPU. Anything else, plain old RISC is simpler.
> To try to keep the subject compilers, instead of comp.arch, it seems
> one should ask what is the best way to get the information that the
> compiler knows about the instructions it is generating into the
> hardware at the time they are needed.
> Out of order execution is needed in case the compiler generated the
> instructions in the wrong order (as needed by the processor).
No. Out of order excution allows you to tackle cases where the best
order is unknowable before runtime including cases where the best
order chnages on everyloop iteration that simply cannot be addressed
by a compiler. It also allows you to work around binary compatibility
between processors and not being able to arbitrarily add new
registers, more predicates and non-blocking loads / stores and have
old software take advantage of such.
> On the other hand, the idea of an architecture independent of the
> implementation only makes sense if you can compile without knowing the
> specific implementation.
> (Remember that machines IBM is building today will still execute
> programs compiled or assembled 40 years ago for S/360.)
> It seems that VLIW, even more than RISC, requires the compiler to know
> too much about implementation details.
RISC does not really expose any more implementation details than CISC,
possibly less - exposure of branch delay slots is a mistake in some
> Otherwise, I don't believe that a VLIW compiler written today could be
> expected to generate code to run on a machine built 40 years from now.
But that severly limits where such a processor will get used.
+++ Out of cheese error +++
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