|scanning/parsing technics for background code analysis in code editor email@example.com (Eric Delage) (2002-07-31)|
|Re: scanning/parsing technics for background code analysis in code firstname.lastname@example.org (jacob navia) (2002-08-04)|
|From:||"jacob navia" <email@example.com>|
|Date:||4 Aug 2002 11:19:09 -0400|
|Organization:||Wanadoo, l'internet avec France Telecom|
|Posted-Date:||04 Aug 2002 11:19:08 EDT|
It is surely not easy.
I did it for my IDE in lcc-win32.
Basically, at each letter typed in, I see if it is a "sensible" key,
and if it is, I rescan the whole file.
A full answer would be too long to be given in a newsgroup.
"Eric Delage" <firstname.lastname@example.org> wrote in message
> I would like to develop a small text editor for VHDL / VerilogHDL with
> features similar to the ones offered by MS Visual Studio for C /
> C++. In particular, I would like to analyze the code in background in
> order to offer code completion/indentation, syntax
> checking/highlighting, pre-compilation, ... while the developper is
> capturing the code.
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