rescheduling VLIW compilation

Ramshankar Ram <>
9 Mar 2002 03:01:32 -0500

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From: Ramshankar Ram <>
Newsgroups: comp.compilers
Date: 9 Mar 2002 03:01:32 -0500
Organization: College of Engineering, University of Massachusetts
Keywords: optimize, parallel
Posted-Date: 09 Mar 2002 03:01:32 EST


I am looking to sequentialize a set of scheduled assembly statements
with parallelism information.

The compiler is constrained to perform only the following
optimizations: control-flow graph simplification, register allocation,
loop rotation and unused code elimination. If anybody is interested,
the compiler is the code composer studio of Texas Instruments for the
C62X VLIW DSP. It is a parallelising compiler as the architecture is
VLIW with no hardware control logic. The compiler also performs a type
of scheduling, I believe called Meld Scheduling, by scheduling
instructions in delay slots of slower instructions.

I have written a parser that goes though the scheduled code and obtains
information like read/write cycle times and can print a dependency

It so happens that the register allocation technique eliminates
redundant writes causing dependencies with assembly statements that
occur in the future in the original source sequence.

Ideas will be greatly appreciated.

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