Re: Branch prediction hints in an ISA

"David Thompson" <david.thompson1@worldnet.att.net>
18 Oct 2000 23:49:35 -0400

          From comp.compilers

Related articles
[2 earlier articles]
Re: Branch prediction hints in an ISA peter_flass@my-deja.com (2000-10-12)
Re: Branch prediction hints in an ISA djimenez@cs.utexas.edu (2000-10-12)
Re: Branch prediction hints in an ISA Kahrs.Juergen@stn-atlas.de (Juergen Kahrs) (2000-10-12)
Re: Branch prediction hints in an ISA erik@arbat.com (Erik Corry) (2000-10-12)
Re: Branch prediction hints in an ISA vbdis@aol.com (2000-10-12)
Re: Branch prediction hints in an ISA zs@ender.cs.mu.oz.au (2000-10-15)
Re: Branch prediction hints in an ISA david.thompson1@worldnet.att.net (David Thompson) (2000-10-18)
Re: Branch prediction hints in an ISA anton@mips.complang.tuwien.ac.at (2000-10-18)
Re: Branch prediction hints in an ISA dietrich@216.26.55.26 (Dietrich Epp) (2000-10-19)
Re: Branch prediction hints in an ISA torbenm@diku.dk (2000-10-19)
| List of all articles for this month |

From: "David Thompson" <david.thompson1@worldnet.att.net>
Newsgroups: comp.compilers
Date: 18 Oct 2000 23:49:35 -0400
Organization: AT&T Worldnet
References: 00-10-078 00-10-103
Keywords: architecture

VBDis <vbdis@aol.com> wrote :
....
> I also remember "delayed" jumps in some machine architecture. This means that
> one (or more?) instructions can be executed after a (conditional) jump
> instruction, while the processor can start to fetch instructions from the
> actual continuation address.
....
> [SPARC has delayed branch, the instruction after a branch is always executed
> to fill an execution pipeline slot. I don't know any new designs that do
> that, out of order execution makes that hack pretty unhelpful. -John]


MIPS has (had) a delay slot for branches and loads (and a few
weirdos); although normally that insn is executed before the branch
successor, the branch can optionally nullify if the branch is not
taken.


IME explicit pipelining, including delayed branches, is more common in
microarchitectures, which is usually an issue for chip/CPU makers
since they are the only microcode writers, although some machines have
allowed user-written microcode (my favorite was the LSI-11/2).


I agree OOO (and speculation) has pretty much obsoleted this.


--
- David.Thompson 1 now at worldnet.att.net


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