Call For Participation - International Symposium on System Synthesis (ISSS 99)

                                                            CALL FOR PARTICIPATION


                                            12th International Symposium on System Synthesis
                                                      DoubleTree Hotel, San Jose, CA, USA
                                                                    November 10-12, 1999


                                                          http://www.eng.uci.edu/~isss99
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Co-sponsored by the IEEE Computer Society and ACM/SIGDA.
With support from the UCI Center for Embedded Computer Systems And Y
Explorations, Inc.


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ISSS'99 is the 12th in a very successful series of symposia oriented
towards professionals in design automation and system level
design. The symposium provides the ideal forum for discussions on the
latest technologies and results in areas of system level design and
synthesis. This year's ISSS will be co-located with ICCAD in the same
hotel. ICCAD's technical sessions will be Nov. 7-10 while ISSS's
technical sessions will start on the afternoon of Wed. Nov. 10. The
Wednesday (Nov. 10) afternoon sessions of ISSS will be integrated in
the ICCAD afternoon program (in one of the ICCAD tracks) and will
contain special topics. Registrants for either ICCAD or ISSS will be
allowed to attend the joint Wednesday afternoon sessions. Thursday and
Friday (Nov. 11-12) will be devoted to the normal ISSS paper
presentations (for ISSS registrants only) separately of ICCAD. Topics
covered in the Symposium include:


· System-level synthesis
· Hardware-software co-design
· Programmable (multi-) processor-based design and synthesis
· System design experience and methodologies.
· Embedded and real-time system software
· High-level and architectural synthesis
· Synthesis for low power, testability and verifiability in the above areas.


In addition to the technical papers presented by leading system-level
CAD researchers and practitioners, this year's ISSS features an
exciting array of special sessions. Several invited speakers from
industry will discuss system-level applications and trends. Embedded
tutorials are presented on Java compilation technology and software
for real-time systems. Finally, a panel on system level design tools
will include key experts from leading system level design houses to
discuss the current state-of-the-art design and corresponding tool
needs. Authors of papers accepted for ISSS'99 and other conferences
are encouraged to submit an extended version of their papers for
possible inclusion in a Special Section of the IEEE Transactions on
VLSI on System Level Synthesis and Design. Submissions of relevant
work not presented at ISSS'99 are also welcome. The call for papers
will be posted on the ISSS'99 Website.


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                                                                        Advance Program
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                                                            Wednesday, November 10, 1999
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9:00am - 12:00 Registration
1:50pm Welcome and Opening Remarks: Allen C.-H. Wu


2:00pm Session 1: Invited Talks Chair: Nikil Dutt, UCI
                1.1 DESIGN OF A SET-TOP BOX SYSTEM ON A CHIP.
                                  Presenter: Eric Foster, IBM Research


                1.2 ON THE RAPID PROTOTYPING & DESIGN OF A WIRELESS
                            COMMUNICATION SYSTEM ON CHIP.
                                  Presenter: Brian Kelley, Motorola.


3:30pm Break


4:00pm Session 2: Embedded Tutorial : JAVA COMPILATION TECHNOLOGY
                    Presenters: Brian Barry & John Duimovich,
                                                          Object Technology International


6:00pm Panel: SYSTEM-LEVEL DESIGN: THE DESIGNERS' WISH LIST VS. REALITY
                    Organizers/Moderators: Dan Gajski & Reinaldo Bergamaschi
                    Panelists: M. Franz, Toshiba America;
                                                        W. Lee, IBM;
                                                        K. Vissers, Philips;
                                                        J. Kunkel, Synopsys;
                                                        G. Martin, Cadence;
                                                        A. Horak, Motorola.




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                                                            Thursday, November 11, 1999
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8:30am Breakfast


9:30am Session 3: Invited Talk: MEMS: MINIATURIZATION BEYOND
MICROELECTRONICS
                                  Presenter: Nadim Maluf, Lucas NovaSensors & Stanford Univ.


10:30am Break
11:00am Session 4: Embedded Tutorial: MIDDLEWARE TECHNIQUES & OPTIMIZATIONS
FOR
                                                                            REAL-TIME EMBEDDED SYSTEMS
                    Presenter: Douglas S. Schmidt, Washington Univ. St. Louis.


12:30pm Lunch


2:00pm Session 5: Real-time & Low Power System design Chair: Pai Chou, UCI
                5.1 EVENT-DRIVEN POWER MANAGEMENT OF PORTABLE SYSTEMS
                                        T. Simunic & G. De Micheli, Stanford U.,
                                        L . Benini, DEIS U. of Bologna


                5.2 REAL-TIME TASK SCHEDULING FOR A VARIABLE VOLTAGE PROCESSOR
                                        T. Okuma, T. Ishihara, & H. Yasuura, Kyushu Univ.


                5.3 PATH-BASED EDGE ACTIVATION FOR DYNAMIC RUN-TIME SCHEDULING
                                        V. Mooney, Georgia Inst. Of Tech.


3:30pm Break & Poster Discussion


4:00pm Session 6: Performance Issues in System Design Chair: TBA


                6.1 OPTIMIZED SYSTEM SYNTHESIS OF COMPLEX RT LEVEL BUILDING BLOCKS
                        FROM MULTIRATE DATAFLOW GRAPHS
                                          J. Horstmannshoff & H. Meyr, Aachen Univ. of Tech.


                6.2 RTGEN: AN ALGORITHM FOR AUTOMATIC GENERATION OF RESERVATION
TABLES
                        FROM ARCHITECTURAL DESCRIPTIONS
                                          P. Grun, A. Halambi, N. Dutt, & A. Nicolau UC Irvine


                6.3 PRE-FETCHING FOR IMPROVED CORE INTERFACING
                                          R. Lysecky, F. Vahid, R. Patel, & T. Givargis, UC
Riverside


                6.4 COMPRESSED CODE EXECUTION ON DSP ARCHITECTURES
                                          P. Centoducatte, R. Pannain, & G. Araujo IC-UNICAMP


5:30pm Free time


7:30pm Banquet


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                                                            Friday, November 12, 1999
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8:30am Breakfast


9:00am Session 7: Memory Design for Embedded Systems Chair: TBA
                7.1 LOOP SCHEDULING AND PARTITIONS FOR HIDING MEMORY LATENCIES
                                  F. Chen & E. H.-M. Sha, Univ. of Notre Dame


                7.2 LOOP ALIGNMENT FOR MEMORY ACCESSES OPTIMIZATION
                                A. Fraboulet, G. Huard, & A. Mignotte, LIP-ENS-Lyon


                7.3 A BUFFER MERGING TECHNIQUE FOR REDUCING MEMORY REQUIREMENTS OF
SYNCHRONOUS
                        DATAFLOW SPECIFICATIONS
                                P. Murthy, Angeles Design Sys & S. S. Bhattacharyya, U. of
Maryland


                7.4 EXPLORATION AND SYNTHESIS OF DYNAMIC DATA SETS IN TELECOM
NETWORK APPLICATIONS
                                C. Ykman-Couvreur, J. Lambrecht, D. Verkest, F. Catthoor, &
H. De Man, IMEC


10:30am Break & Poster Discussion


11:00am Session 8: Architectural Synthesis Chair: TBA


                8.1 A GRAPH THEORETIC APPROACH FOR DESIGN AND SYNTHESIS OF
MULTIPLIERLESS FIR
                        FILTERS.
                                K. Muhammad, & K. Roy, Purdue Univ.


                8.2 EFFICIENT SCHEDULING OF DSP CODE ON PROCESSORS WITH DISTRIBUTED
                        REGISTER FILES
                                B. Messman, Philips Labs, C. Alba Pinto, & K. van Eijk,
Eindhoven Univ. of Tech.


                8.3 AUTOMATIC ARCHITECTURAL SYNTHESIS OF VLIW AND EPIC PROCESSORS
                                S. Aditya, B. Ramakrishna Rau, & V. Kathail, HP Labs


                8.4 BIT-WIDTH SELECTION FOR DATA-PATH IMPLEMENTATIONS
                                C. Carreras, J. A. Lopez, & O. Nieto, UPM


12:30pm Lunch


2:00pm Session 9: System Design Methodologies Chair: TBA


                9.1 CATALYST: A DSIP DESIGN FLOW DEVELOPMENT IN INDUSTRY
                                W. De Rammelaere, R.McGarity, F. Steininger, P. Le Moenner,
                                E.Hilkens, Motorola SPS


                9.2 SYSTEM SYNTHESIS OF SYNCHRONOUS MULTIMEDIA APPLICATIONS
                                G. Qu, M. Maserina, & M. Potkonjak, UCLA


                9.3 A FRAMEWORK FOR SCHEDULING AND CONTEXT ALLOCATION IN
RECONFIGURABLE COMPUTING
                                R. Maestre, M. Fernandez, R. Hermida, UCM, & N.
Bagherzadeh, UC Irvine


3:30pm Break & Poster Discussion


4:00pm Concluding Remarks: Allen C.-H. Wu & Fadi J. Kurdahi


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                                                                      Symposium Registration
---------------


Please complete the form and send (or fax) it with payment to:


Fadi J. Kurdahi, Program Chair ISSS'99
ECE Department, Engineering Tower, Room 516C
University of California
Irvine, CA 92697-2625
U.S.A.
Tel: +1 (949) 824-8104
Fax: +1 (949) 824-2321
Email: kurdahi@ece.uci.edu


Registration fee: (includes breaks, breakfast & lunch on Nov 11, 12, & Nov
11 Banquet).


                                                                          (please circle one)
STATUS BY SEPTEMBER 30, 1999 AFTER SETEMBER 30, 1999
ACM/IEEE Members $350 $ 425
Non-Members $425 $ 500
Full-time Students $275 $ 325


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Payments with registration must be made in U. S. Dollars and drawn
from a U. S. bank. Make checks payable to: ISSS'99.


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                                                                            Venue Information
--------------


HOTEL INFORMATION


ISSS'99 will take place in the DoubleTree Hotel in San
Jose. Accommodation is in the same hotel as foreseen. Make
reservations directly with the DoubleTree Hotel by calling the
toll-free number: +1 (800) 222-8733, mentioning ICCAD to obtain the
special low rates. The conference rate of $125/$135 per night
(single/double occupancy) is guaranteed until October 4, 1999 after
which reservations will be based on availability.


GETTING THERE


Located in the heart of the Silicon Valley, the Doubletree Hotel
(formerly Red Lion Hotel) San Jose is only minutes from the San Jose
International Airport and 35 minutes south of the San Francisco
International Airport. Convenient shuttle service is available from
the San Jose Airport to the Doubletree Hotel. To get a courtesy
shuttle from the airport, pick up a courtesy phone in the baggage
claim area and call the hotel.


SHUTTLE SERVICE FROM SAN FRANCISCO AIRPORT


For travel information from the San Francisco Airport to the
Doubletree Hotel San Jose, you may contact the BayPorter Express at:
(415) 467-1800 or the Super Shuttle at: (415) 558-8500.


ADDRESS


Doubletree Hotel San Jose
2050 Gateway Place
San Jose, CA 95110
USA


Phone: +1 (408) 453-4000 or +1 (800)-222-TREE
Fax: +1 (408) 437-2898


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                                                                  Steering Committee
----------------
General Chair: Allen C.-H. Wu, Tsing Hua U., TAIWAN
Program Chair: Fadi J. Kurdahi, U. C. Irvine, USA
Special Sessions Chair: Reinaldo Bergamaschi, IBM, USA
Publicity/Publications Chair: Loganath Ramachandran, Angeles Design Sys.,
USA
Liaison with ICCAD: Nikil Dutt, U.C. Irvine, USA
Local Arrangements/Finance Chair: Sanjiv Narayan, Cadence, USA
Past Chair: Francky Catthoor, IMEC, BELGIUM


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                                                        Technical Program Committee
----------------
Gaetano Borriello, U. Washington, USA
Raul Camposano, Synopsys, USA
Rolf Ernst, Tech. U. Braunschweig, GERMANY
Masahiro Fujita, Fujitsu, JAPAN
Daniel Gajski, U.C. Irvine, USA
Roman Hermida, UCM, SPAIN
Yu-Chin Hsu, Avant! Corp., USA
Ahmed A. Jerraya, TIMA, FRANCE
Kayhan Kucukcakar, Escalade, USA
Steve Y.L. Lin, Tsing Hua U., TAIWAN
Paul Lippens, Philips, NETHERLANDS
Jan Madsen, Tech. U. DENMARK
Gjalt de Jong, Alcatel, BELGIUM
Lev Markov, Mentor Graphics, USA
Peter Marwedel, U. Dortmund, GERMANY
Vijay Nagasamy, Arithmos Inc., USA
Walid Najjar, Colorado State U., USA
Yukihiro Nakamura, Kyoto Univ., JAPAN
B. Ramakrishna (Bob) Rau, HP Labs., USA
Wolfgang Rosenstiel, U. Tubingen/FZI GERMANY
Leon Stok, IBM, USA
Donald Thomas, CMU, USA
Frank Vahid, U.C. Riverside, USA
Diederik Verkest, IMEC, BELGIUM
Kazutoshi Wakabayashi, NEC, JAPAN
Robert Walker, Kent State U., USA
Wayne Wolf, Princeton U., USA
Hiroto Yasuura, Kyushu U., JAPAN
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