Binary Translation Workshop - Submission Deadline Extended

... DEADLINE EXTENDED ... DEADLINE EXTENDED ... DEADLINE EXTENDED ...
          August 2, 1999 August 2, 1999 August 2, 1999


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                                                            CALL FOR PAPERS
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                                                Workshop on Binary Translation


                        In Conjunction with the International Conference on
              Parallel Architectures and Compilation Techniques (PACT '99)
                                            http://www.rose-hulman.edu/PACT/


                              Newport Beach, California, USA October 16, 1999


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OBJECTIVE
---------
Although long employed by industry, large scale use of binary
translation and on-the-fly code generation has only recently become
common, and results have been published in widely scattered
publications.


The main objective of this workshop is to bring together researchers
and practitioners with the aim of stimulating the exchange of ideas
and experiences on the potential and limits of binary translation, and
opening new avenues of research.


SUBMISSIONS
-----------
Papers due August 2th, 1999.


Notifications of acceptance by Sept. 10th, 1999.


Final papers (maximum of 10 pages) due Sept. 25th, 1999. You can
choose any format for the final version of accepted papers. The only
restriction is that the paper should be (1) ghostviewable, (2) in
PostScript, and (3) printable on USLetter (8.5 x 11 inch page) sized
paper. More detailed submission guidelines are provided below.


Questions: yaron.sheffer@intel.com or erik@watson.ibm.com


NOTE: Only electronic submissions will be accepted!


Proceedings will be published in the IEEE TCCA Newsletter and selected
papers will be invited to submit to a special issue of a top journal
publication.


KEYNOTE ADDRESS
---------------
Dick Sites, architect of the DEC/Compaq Alpha and leader of the FX!32,
VEST, and mx binary translation projects will present a 1 hour keynote
address on "Historical Perspectives on Binary Translation".


WORKSHOP REGISTRATION
---------------------
Registration: There may be a nominal registration fee for the
Binary Translation Workshop, in addition to the fee to register
for the PACT'99 conference. Until details and formal registration
procedures are determined, please indicate your interest in
registering for the workshop by sending email to:


      yaron.sheffer@intel.com or erik@watson.ibm.com


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DETAILS
-------
This workshop is intended to be a forum for bringing together
researchers in the area of binary translation. Talks will be solicited
emphasizing new ideas and experience with building binary translation
systems. There will be a limited number of talks in order to allow the
audience to participate. The topics of interest include, but are not
limited to:


    -- Dynamic (Runtime) Translation
                o With operating system support
                o Without operating system support
                o Java
                o From traditional architectures such as Alpha, IA32, MIPS,
                    PowerPC, and SPARC to new architectures


    -- Static Translation
                o With no runtime assistance/translation
                o With runtime assistance/translation (Hybrid Translation)


    -- General techniques and problems
                o Compatibility
                      * Self-modifying code
                      * Self-referential code
                      * Precise exceptions
                      * Other issues
                o Scheduling and optimization
                o Adapting code to changing program behavior
                o On-the-fly reconstruction of CFG's and data dependences
                o Management of translated code
                o Other compilation challenges


    -- Hardware Support
                o Hardware Assists for Binary Translation
                      * Interpretation Engines
                      * Profiling Branch Directions, Instructions with Cache Misses,
                          etc.
                      * Other Assists


                o Hardware Mechanisms Employing Binary Translation Techniques
                      * Pipeline cracking CISC operations into micro-ops,
                          a la Pentium Pro
                      * Cached hardware schedules a la DIF
                      * Other Mechanisms


DETAILED SUBMISSION GUIDELINES
------------------------------


Talks will be accepted on the basis of a short paper that describes
the work and the novel algorithms or experiences that resulted from
it.


Please prepare your paper as plain ASCII PostScript only, with NO
encoding, condensing, or encapsulation. Please use TrueType 1 fonts
wherever possible. Do not use bitmapped fonts such as Computer Modern
if you can avoid it. Please include the following information in plain
text with the submitted paper: (1) Author's Name(s), (2) Postal
Address, (3) Phone Number, (4) FAX Number, (5) Email Address, (6)
Title of Paper,(7) 5 Keywords, and (8) Abstract. Hard copy (postal)
submissions will not be accepted.


Papers should be at most 10 pages in length, with a maximum of 6 pages
of text. The remainder may be tables, figures, and references. (Tables
and Figures need not be at the end of the paper. They can and should
be interspersed with text.) Papers should also be displayable and
printable from ghostview. Please send email to yaron.sheffer@intel.com
or erik@watson.ibm.com if these requirements are a hardship.


Please email submissions to erik@watson.ibm.com by August 2. You
should receive a notification of your submission by the following
week. Authors will be notified of acceptance or rejection by
September 10, and the final version of accepted papers are due
September 25.


All submissions will be refereed, and workshop attendees will receive
copies of all accepted papers.


ORGANIZERS
----------
Workshop Co-Chairs: Yaron Sheffer (Intel) and Erik Altman (IBM)


Program Committee:
------------------
Brad Calder University of California - San Diego
Evelyn Duesterwald HP Labs
Kemal Ebcioglu IBM T.J. Watson Research
Michael Franz University of California - Irvine
Michael K. Gschwind IBM T.J. Watson Research
Ray Hookway Compaq
David Kaeli Northeastern University
David Keppel Transmeta
Andreas Krall Technical University of Vienna
James R. Larus Microsoft Research
David J. Lilja University of Minnesota
Soo-Mook Moon Seoul National University
Sumedh Sathaye IBM T.J. Watson Research
Michael Smith Harvard University

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