The Journal of Instruction-Level Parallelism Call for Papers

        The Journal of Instruction-Level Parallelism Call for Papers


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The Journal of Instruction-Level Parallelism (JILP) is a Web-first,
paper-based archival journal dedicated to soliciting, thoroughly
reviewing, and publishing state-of-the-art papers in all areas of
instruction-level parallelism (ILP.) JILP encourages submission of all
types of archival-quality material from both the hardware and software
fields of fine-grained parallelism. The journal being Web-first is
dedicated to the rapid review and dissemination of articles submitted.


Example topic areas of particular relevance include the following:
o High-performance microarchitecture innovation: VLIW, superscalar,
multithreaded, etc.
o Compiler techniques for exploiting instruction-level parallelism:
software pipelining, global scheduling, register allocation,
memory disambiguation, etc.
o Branch prediction hardware and software.
o Value prediction hardware and software.
o Object code translation hardware and software (static or dynamic.)
o Hardware/compiler techniques for improving memory system performance.
o Hardware/software techniques for fine-grain parallel processing.
o Theoretical foundations of instruction-level parallelism and/or fine
-grain parallelism.
o Design Automation special support for the high-performance/ILP
microarchitecture domain.
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Please see the web site at http://www.jilp.org for further details.
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                                                Co-Editors-in-Chief:
Tom Conte, NCSU Matthew Farrens, UC Davis
                                                    Editorial Board:
Steven Beaty, MSCD Robert Colwell, Intel
Joseph Fisher, HP Wen-Mei Hwu, UIUC
Bill Mangione-Smith, UCLA Yale Patt, Univ. of Mich.
B. Ramakrishna Rau, HP James E. Smith, Univ. of Wisc.
Gary Tyson, Univ. of Mich. Mark Smotherman, Clemson
Gurindar Sohi, Univ. of Wisc.

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