CONFERENCE: ISSS'98 Advance Registration Extention (matrix)
30 Oct 1998 13:57:08 -0500

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CONFERENCE: ISSS'98 Advance Registration Extention (1998-10-30)
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From: (matrix)
Newsgroups: comp.compilers
Date: 30 Oct 1998 13:57:08 -0500
Organization: Dept. of Computer Science, Nat'l Tsing Hua Univ., Taiwan, R.O.C.
Keywords: conference

RE: Advance Registration Extention to Nov. 6.

                                    Hsinchu, Taiwan, R.O.C., December 2-4, 1998
                    Sponsored by the IEEE Computer Society DATC and the ACM SIGDA

                                                        FINAL PROGRAM

Tuesday, December 1, 1998

18:00 - 20:00 On-site Registration

19:00 - 21:00 Reception

Wednesday, December 2, 1998

08:30 - 09:00 Open statement

09:00 - 10:00 Invite talk:
                                Is IP Business Hype or Reality?
                                D. D. Gajski, U. of California, Irvine, USA

10:00 - 10:30 Coffee break

10:30 - 11:30 Session 1:
                                Code Generation and Optimization Issues

                                1.1 A Uniform Optimization Technique for Offset Assignment
                                        Rainer Leupers, Fabian David; Dept. of Computer Science,
                                        Univ. of Dortmund

                                1.2 Code Generation for Compiled Bit-True Simulation of DSP
                                        L. De Coster, M. Ade, R. Lauwereins, J.A. Peperstraete;
                                        Katholieke Univ. Leuven, Dept. ESAT, Belgium

                                1.3 Addressing Optimization for Loop Execution Targeting DSP
                                        with Auto-Increment/Decrement Architecture
                                        W.-K. Cheng, Y.-L. Lin; Dept. of CS, NTHU, Taiwan, R.O.C

11:30 - 12:00 Poster discussion

12:00 - 13:30 Lunch

13:30 - 14:30 Invite talk:
                                Issues in Embedded DRAM Development and Applications;
                                K.-S. Doris; Siemens Research and Devel, Germany

14:30 - 15:30 Session 2:
                                IP Reuse and Language

                                2.1 A Processor Description Language Supporting Retargetable
                                        Multi-Pipeline DSP Program Development Tools
                                        C. Siska; Rockwell Semiconductor Systems, Inc.

                                2.2 Intellectual Property Re-use in Embedded System Co-design:
                                        an Indutrial Case Study
                                        E. Filippi, L. Lavagno, L. Licciardi, A. Montanaro,
                                        M. Paolini, R. Passerone, A. Sangiovanni-Vincentelli,
                                        M. Sgroi; CSELT, Italy. Dipartimento di Elettronica,
                                        Politecnico di Torino, Italy. Univ. of CA. at Berkeley,

                                2.3 Incorporating Cores into System-Level Specification
                                        F. Vahid and T. Givargis; Dept. of Computer Science,
                                        Univ. of California, USA

15:30 - 16:00 Poster discussion and coffee break

16:00 - 16:30 Poster presentation

                                P1 HDL-Based Modeling of Embedded Processor Behavior for
                                      Retargetable Compilation
                                      R. Leupers; Dept. of Computer Science, Univ. of Dortmund

                                P2 False Path Analysis based on a Hierarchical Control
                                      A. A. Kountouris and C. Wolinski; IRISA -
                                      Institut de Recherche en Informatique et Systemes Aleatoires

                                P3 Resource constrained Modulo Scheduling with Global Resource
                                      C. Jaeschke, R. Laur; Univ. of Bremen, Dept. 1, Institute of
                                      Electromagnetic Theory and Micro., Bremen/Germany.

                                P4 Statistical Performance-Driven Module Binding in High-Level
                                      H. Tomiyama, A. Inoue, and H. Yasuura; Dept. of Computer
                                      Science and Communication Eng., Graduate School of
                                      Information Science and Electrical Eng., Kyushu Univ., Japan

                                P5 Concurrent Error Detection at Architectural Level
                                      C. Bolchini, W. Fornaciari, F. Salice, D. Sciuto;
                                      Cristiana Bolchini: Politecnico di Milano-Dipartimento di
                                      Elettronica e Informazione, Italy.

                                P6 Communication and Interface Synthesis on a Rapid Prototyping
                                      Hardware/Software Codesign System
                                      Y.-T. Hwang, Y.-H. Wang; Dept. of Electronic Eng. NYU of
                                      Science & Technology Taiwan, R.O.C

16:30 - 17:30 Poster discussion

18:30 - 20:00 Dinner

20:00 - 22:00 Panel:
                                IP-Based design: VIP (Very Important Process) or
                                  RIP(Rest in Peace)

Thursday, December 3, 1998

09:00 - 10:00 Invite talk:
                                Compiler Technology for Application-Specific Processors/Systems
                                on Chips
                                Monica Lam, Stanford Univ., USA

10:00 - 10:30 Coffee break

10:30 - 11:30 Session 3:
                                Application-Specific Synthesis Techniques

                                3.1 Application-Specific Heterogenous Multiprocessor Synthesis
                                        Using Differential-Evolution
                                        A. Rae, S. Parameswaran; Dept. of Computer Science and
                                        Electrical Eng. Univ. of Qu`ensland, Australia.

                                3.2 Proposal for unified system design meta flow in task- level
                                        and instruction-level design technology research for
                                        multi-media applications
                                        F. Catthoor, D. Verkest, E. Brockmeyer; IMEC, VSDM Division,
                                        Katholieke Univ. Leuven

                                3.3 Data-path Synthesis of VLIW Video Signal Processors
                                        Z. Wu, W. Wolf; Dept. of Electrical Eng., Princeton Univ.,

11:30 - 12:00 Poster discussion

12:00 - 13:30 Lunch

13:30 - 14:30 Group Discussion

14:30 - 15:30 Session 4:
                                Synchronization and Interface Issues

                                4.1 Synchronization Detection for Multi-Process Hierarchical
                                        O Bringmann, W. Rosenstiel, D. Reichardt; FZI and Univ. of
                                        Tubingen, Germany

                                4.2 Integrating Communication Protocol Selection with
                                        Partitioning in Hardware/Software Codesign
                                        P. V. Knudsen and J. Madsen; Dept. of Information Technology,
                                        Technical Univ. of Denmark, Denmark

                                4.3 Interface Exploration for Reduced Power in Core-Based Systems
                                        T. Givargis, F. Vahid; Dept. of Computer Science, University
                                        of California, U.S.A.

15:30 - 16:00 Poster discussion and coffee break

16:00 - 17:00 Session 5:
                                Instruction Encoding and Software Synthesis Techniques

                                5.1 Instruction Encoding Techniques for Area Minimization of
                                        Instruction ROM
                                        T. Okuma, H. Tomiyama, A. Inoue, E. Fajar, H. Yasuura
                                        Dept. of Computer Science and Communication Eng., Kyushu
                                        University, Japan

                                5.2 Application of Instruction Analysis/Synthesis Tools to x86's
                                        Functional Unit Alloation
                                        I.-J. Huang, P.-H. Xie; Institute of Computer and
                                        Information Eng., NSYSU Kaohsiung, Taiwan, R.O.C.

                                5.3 Memory Efficient Software Synthesis from Dataflow Graph
                                        W. Sung, Junedong Kim, Soonhoi Ha; Dept. of Computer Eng.,
                                        Seoul National University, Korea

17:00 - 17:30 Poster discussion

17:30 - 18:30 General discussion session

19:00 - 21:00 Banquet

Friday, December 4, 1998

09:00 - 10:00 Invite talk:
(Subject: TBA)
Min Wu, Maronix International. Co. Ltd.

10:00 - 10:30 Coffee break

10:30 - 11:30 Session 6:
                                Partitioning and Scheduling Techniques

                                6.1 A Tool Partitioning and Pipelined Scheduling of Hardware-
                                        Software Systems
                                        Karam S. Chatha and Ranga Vemuri; Laboratory for Digital
                                        Design Environments, Department of ECECS, University of

                                6.2 A Three-Step Approach to the Functional Partitioning of
                                        Large Behavioral Processes
                                        F. Vahid; Dept. of Computer Science, Univ. of California,

                                6.3 Fine-Grain, Incremental Rescheduling Via Architectural
                                        Retiming; S. Hassoun; Dept. of Electrical Eng. and Computer
                                        Science, Tufts University

11:30 - 12:00 Poster discussion

12:00 - 13:30 Lunch

13:30 - 16:30 Science-Based Industry Park Tour

Saturday, December 5, 1998

          Taipei City Tour

Sunday, December 6, 1998

          Tarako National Park Tour

ISSS'98 Registration Form
(Print or Type, one form for each registrant.)
(If your payment is by credit card, please FAX the form to us. Thank you.)
Please enter your session/paper number _________________ for authors.
Advance Registration Deadline: October 25, 1998
Any registration after Oct. 25, 1998 (postmark cut-off) will be charged the
at-symposium rate.
Please complete the information below. Payment with registration must be made
in US or NT dollars and made payable to:

Allen C.-H. Wu
Account No. 036-16-0060160,
Chiao Tung Bank, Hsinchu Branch, Hsinchu, Taiwan.

Title : __Prof. __Dr. __Mr. __Ms. __Miss. __Mrs.

Name : ____________________________________________
                                                Last First Mid
Affiliation : ____________________________________________

Address : ____________________________________________



Phone : ____________________________________________

Fax : ____________________________________________

E-mail : ____________________________________________

Special needs [ ] Vegetarian [ ] Other ________________

      Before Nov. 6, 1998 | After Nov. 6, 1998
[ ]ACM/IEEE Member |
[ ]US$320 [ ]NT$11,000 | [ ]US$380 [ ]NT$13,000
[ ]Non-member |
[ ]US$400 [ ]NT$13,500 | [ ]US$400 [ ]NT$13,500
[ ]Full-time Student |
[ ]US$150 [ ]NT$ 5,000 | [ ]US$200 [ ]NT$6,500
Total Amount Enclosed :

      US$ __________ NT$ ___________
      (or transferred to the above mentioned account)

ACM/IEEE Membership # : _________________
      (reqd. if registering at ACM/IEEE rates)

I __enclose __Traver's check __ Money order
I __use Credit card : __Visa __Master Card

      (Do not accept American Express).

Card No. ___________ - ___________ - ___________ - ___________

Expiry date: __________________________________________________

Name as it appears on card: ___________________________________

Passport no./ROC citizen ID no.:_______________________________

Signature: ___________________________________________________

Date: ________________________________________________________

Cancellation Policy: No refunds will be made on cancellations
received after Nov. 20, 1998. Cancellations received before
Nov. 20 are subject to a 20% processing fee.

Hotel Reservation Form
Please type or print.
Title : __Prof. __Dr. __Mr. __Ms. __Miss. __Mrs.

Name : _______________________________________
                                    Last First Mid

Affiliation: _______________________________________

Address : _______________________________________



Phone : _______________________________________

Fax : _______________________________________

E-mail : _______________________________________

Member of IEEE/ACM Member No.:____________________

    Hotel Single Twin
__Chinatrust Hotel __NT$2,970 __NT$3,330
__Shin Yuan Park Hotel __NT$2,430 __NT$3,120
          (include service charge and tax.)

Check-in date: ___________ Check-in time: _________

Check-out date: ___________ Number of nights: _____

        One way, between the CKS Airport and Hotel: NT$1,300

Flight Number: ___________ Arrival Time: ____________

            Pay to the hotel when you check out with cash, traveler's check, or credit
            card. No personal check, please.

NOTE: The room rates and availability are guaranteed for the period of Nov. 29 -
            Dec. 6, 1998, only if your reservation form is received before Oct. 25,
Please send this form to the hotel you choose:

        Chinatrust Hotel:
            106 Chung Yang Rd., Hsinchu, Taiwan 300
            Fax: +886-3-5269244; Tel: +886-3-5263181

        Shin Yuan Park Hotel:
            11 Ta Tung Rd., Hsinchu, Taiwan 300
            Fax: +886-3-5260522; Tel: +886-3-5226868

Tour Reservation Form
Tour 1.: Taipei City Tour
Date: Dec. 5, 1998 (Sat.)
Fare: NT$1,750(Includes: 1 lunch)
        1. National Palace Museum
        2. Martyr's Shrine
        3. Chinese Temple
        4. Chiang Kai-Shek Memorial Hall
        5. Dr. Sun Y. S. Memorial Hall
        6. Presidential Office (Pass by)
        7. Handicraft Center
Tour 2.: Tarako National Park (Hualien)
Date: Dec. 6, 1998 (Sun.)
Fare: NT$4,200 (Including: Round-trip air ticket and lunch)
              (Passport needed for enplaning)
Itinerary: Pick-up from hotel -> Transfer to Taipei Airport ->
                        Arrive at Hualien -> Enbus for Tarako Groge Gateway
                        ->Eternal-Spring Shrine -> Swallow Caves -> Tunnel of
                        Nine Turns -> TienhsiangLodge -> Marble factory ->
                        Enplane for Taipei -> Transfer to hotel

Please type or print.
Sex: __F __M

Name : _______________________________________________
                                    Last First Mid

Passprot No.: ____________________________________

Birth Date : ____________________________________

Nationality : ____________________________________

Signature : ____________________________________
Tour Selection: please indicate your choice(s)
    ___ Taipei City Tour ____Tarako National Park (Hualien)

Total amount: NT$______________________

Payment: By cash or traverler's check in NTD to the travel agent at the
conference site.
Please send this form to (before Oct. 25, 1998)
      Trans Continental Travel Service Co., Ltd.
      4F, No. 21, Lane 45, Sec. 2, Chung-San N. Rd.,
      Taipei, Taiwan.
      Fax: +886-2-25230002; +886-2-26946057
      Tel: +886-2-25233131

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