code generation for the x86 FPU?

I'm looking for information (articles, papers, etc.) on how to perform
high-quality code generation and register allocation for the stack-
oriented Intel x86 floating-point unit.


My current "paper" design is to generate code and do register
coalescing, allocation, and spilling as if the FPU had 8 normal FP
registers. Then I translate these virtual instructions to actual x86
ones using a simulated stack to keep track of which virtual FP
registers are on the stack, and in which order. At control-flow
branches I insert new blocks with FXCH instructions to ensure that the
FP stack is in the order expected by the successor block. I'll also do
some optimization of this fixup code.


However, this isn't as nice and tidy as I'd like, so I'd like to
know about other (hopefully simpler) approaches.


Any help on this would be much appreciated.


/Mikael
--
Mikael Pettersson (mikpe@csd.uu.se)
Computing Science Department, Uppsala University
[There's been a fair amount of work on code generation for stack machines,
which I think would be the place to start. -John]
--

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