two ILP compiler technique sessions at MICRO-30 / adv. program

M I C R O - 30


30th Annual International Symposium on Microarchitecture
with special emphasis on Instruction-Level Parallel Processing


MICRO-30 will be held at the Sheraton Imperial Hotel in Research
Triangle Park, North Carolina, from Nov. 30 to Dec. 3. Registration
information is available at the web site
http://www.ece.ncsu.edu/micro30. Advance registrations are due by
Nov. 8. The hotel is approximately one mile from the Raleigh/Durham
(RDU) airport and provides a complimentary shuttle bus to and from the
airport.


Sunday, November 30th


    5:00 PM Registration opens


    7:00-10:00 PM Welcoming Reception


Monday, December 1st


    8:00- 8:30 Welcome


    8:30- 9:30 Keynote Speech - Bob Colwell


"Product Recalls, Acrophobia, and Computer Microarchitecture"


  10:00-12:00 Session 1: Instruction Fetch (chair: Brad Calder)


"The Bi-Mode Branch Predictor"
C. Lee, I. Chen, T. Mudge
"Path-Based Next Trace Prediction"
Q. Jacobson, E. Rotenberg, J. Smith
"Improving Trace Cache Performance by Boosting the Effective Fetch
Rate"
D. Friendly, S. Patel, Y. Patt
"Reducing the Performance Impact of ICache Misses by Writing
Instructions into the Reservation Stations Out-of-Order"
J. Stark, P. Racunas, Y. Patt


  12:00- 1:00 Lunch (provided)


    1:00- 3:00 Session 2: Data Cache Improvements (chair: Jim Bondi)


"On High-Bandwidth Data Cache Design for Multi-Issue Processors"
J. Rivers, G. Tyson, T. Austin, E. Davidson
"Run-time Spatial Locality Detection and Optimization"
T. Johnson, M. Merten, W. Hwu
"A Comparison of Data Prefetching on an Access Decoupled and
Superscalar Machine"
G. Jones, N. Topham
"The Design and Performance of a Conflict-avoiding Cache"
N. Topham, A. Gonzalez, J. Gonzalez
"Prediction Caches for Superscalar Processors"
J. Bennett, M. Flynn


    3:30- 5:30 Session 3: ILP Compiler Techniques I (chair: Jim Dehnert)


"A Framework for Balancing Control Flow and Predication"
D. August, S. Mahlke, W. Hwu
"Evaluation of Scheduling Techniques on a SPARC-Based VLIW Testbed"
S. Park, S. Shim, S. Moon
"Tuning Compiler Optimizations for Simultaneous Multithreading"
J. Lo, S. Parekh, S. Eggers, H. Levy, D. Tullsen
"Exploiting Dead Value Information"
M. Martin, A. Roth, C. Fischer


    8:00-10:00 SIGMICRO/TC-MICRO Business Meeting


Tuesday, December 2nd


    8:00-10:00 Session 4: Novel Microarchitectures (chair: Ilan Spillinger)


"Trace Processors"
E. Rotenberg, Q. Jacobson, Y. Sazeides, J. Smith
"The Multicluster Architecture: Reducing Cycle Time Through
Partitioning"
K. Farkas, P. Chow, N. Jouppi, Z. Vranesic
"Out-of-Order Vector Architectures"
R. Espasa, M. Valero, J. Smith
"Initial Results on the Performance and Cost of Vector
Microprocessors"
C. Lee, D. DeVries


  10:30-12:00 Session 5: Memory for Embedded Processors (chair: Andy Wolfe)


"The Filter Cache: An Energy Efficient Memory Structure"
J. Kin, M. Gupta, W. Mangione-Smith
"Improving Code Density Using Compression Techniques"
C. Lefurgy, P. Bird, I. Chen, T. Mudge
"Procedure Based Program Compression"
D. Kirovski, J. Kin, W. Mangione-Smith


  12:00- 1:30 Lunch (provided) - Speaker: Mike Flynn


"Some Reflections on Computer Engineering: 30 Years After the
360 Model 91"


    1:30- 3:00 Session 6: Load/Store Tuning (chair: Dean Tullsen)


"Improving the Accuracy and Performance of Memory Communication
Through Renaming"
G. Tyson, T. Austin
"Microarchitecture Support for Improving the Performance of Load
Target Prediction"
C. Chen, A. Wu
"Streamlining Inter-operation Memory Communication via Data
Dependence Prediction"
A. Moshovos, G. Sohi


    3:30- 5:30 Session 7: Value Prediction (chair: Nancy Warter-Perez)


"The Predictability of Data Values"
Y. Sazeides, J. Smith
"Value Profiling"
B. Calder, P. Feller, A. Eustace
"Can Program Profiling Support Value Prediction?"
F. Gabbay, A. Mendelson
"Highly Accurate Data Value Prediction using Hybrid Predictors"
K. Wang, M. Franklin


    7:00-11:00 PM Outing to ArtSpace in Raleigh's CityMarket, sponsored by
Intel


Wednesday, December 3


    8:00-10:00 Session 8: Profiling and Benchmarking (chair: Steve Beaty)


"ProfileMe: Hardware Support for Instruction-Level Profiling on
Out-of-Order Processors"
J. Dean, J. Hicks, Waldspurger, Weihl, Chrysos
"Procedure Placement using Temporal Ordering Information"
N. Gloy, T. Blackwell, M. Smith, B. Calder
"Predicting Data Cache Misses in Non-Numeric Applications Through
Correlation Profiling"
T. Mowry, C. Luk
"Available Parallelism in Video Applications"
H. Liao, A. Wolfe
"MediaBench: A Tool for Evaluating Multimedia and Communications
Systems"
C. Lee, M. Potkonjak, W. Mangione-Smith


  10:30-12:00 Session 9: ILP Compiler Techniques II (chair: Scott Mahlke)


"Cache Sensitive Modulo Scheduling"
F. Sanchez, A. Gonzalez
"Unroll-and-Jam Using Uniformly Generated Sets"
S. Carr, Y. Guan
"Resource-Sensitive Profile-Directed Data Flow Analysis for Code
Optimization"
R. Gupta, D. Berson, J. Fang
--
Mark Smotherman, Computer Science Dept., Clemson University, Clemson, SC
http://www.cs.clemson.edu/~mark/homepage.html
--

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