Announcing: PACT-97 Program

                                                                ADVANCE PROGRAM


                                              The 1997 International Conference
                            on Parallel Architectures and Compilation Techniques
                                                          November 10-14, 1997


                                                                  Ramada Hotel
                                                    San Francisco, CA, 94103 USA
                                                          (415) 826-8000 (voice)
                                                          (415) 861-1460 (fax)




                  http://www-iscr.llnl.gov/iscr/projects/crg/pact97/pact97.html


(See the above web site for registration assistance and further
information.)


CONFERENCE OBJECTIVES
Current and future generation computer systems are aggressively pursuing
parallelism for increased performance. As the field matures, the gulf
between hardware and software performance grows larger. The purpose of
this
working conference, the sixth in the series, is to provide an open forum
for the parallel architecture and compiler research communities to debate
key issues of common interest and to discuss how the two communities might
work together to more efficiently exploit the performance of parallel
systems.


At this year's meeting, there will be a number of technical sessions,
keynote speeches, and tutorials that address these matters. We invite
researchers and practitioners with interests in both conventional and
non-conventional approaches (MPP, SMP, clustered-SMP, data-flow,
multi-threading, and optical) to participate in the following program:


KEYNOTE SPEECHES


Wednesday, November 12, 1997
Computing comes of age: Deep Blue vs. Kasparov
Dr. A. Joseph Hoane, Jr.
T.J. Watson Research Center


Thursday, November 13, 1997
Concurrent Design of a Compiler and an Architecture
Dr. Burton Smith
Tera Computer Company


Friday, November 14, 1997
The Challenge of Supporting Architecture-Indepedent Programming
on Parallel and Distributed Computer Systems
Dr. Ken Kennedy
Rice University


TUTORIAL PROGRAM
Tuesday, November 11, 1997


1. Java Programming and Compilation;
      Milind Girkar, Intel Corporation;
      full day.


2. Instruction Level Parallel Processing:
      Architectures and Code Generation;
      Dr Henk Corporaal, Delft University of Technology;
      full day.


3. Distributed Discrete Simulation: Opportunities and Pitfalls;
      Dr. ir. Erik Dirkx, Vrije Universiteit Brussel;
      half day (morning).


4. Distributed Shared Memory: Concepts and Systems - The 1997 Update;
      Jelica Protic, Milo Tomasevic, Veljko Milutinovic, IFACT;
      half day (afternoon).


TECHNICAL PROGRAM


Monday, November 11
1500 - 1700 - Tutorial registration


Tuesday, November 12
0830 - 1000 - Tutorial, first morning session
1000 - 1030 - Break
1030 - 1200 - Tutorial, second morning session
1200 - 1330 - Lunch
1330 - 1500 - Tutorial, first afternoon session
1500 - 1530 - Break
1530 - 1700 - Tutorial, second afternoon session
1500 - 1700 - Conference registration
1800 - 2100 - Reception


Wednesday, November 13
0800 - 0830 - Continental Breakfast
0830 - 1000 - Keynote Speech I
1000 - 1030 - Break
1030 - 1200 - Session I. Analysis and Code Optimizations
1) Locality Analysis for Parallel C Programs;
      Yingchun Zhu and Laurie J. Hendren;
      McGill University.
2) Heap Analysis and Optimizations for Threaded Programs;
      Xinan Tang, Rakesh Ghiya, Laurie J. Hendren, and Guang R. Gao;
      McGill University and University of Delaware.
3) Interprocedural Distribution Assignment Placement:
      More Than Just Enhancing Intraprocedural Placing Techniques;
      Jens Knoop and Eduard Mehofer;
      Universitat Passau and Universitat Wien.
1200 - 1330 - Lunch
1330 - 1500 - Session II. Networks/Communication Optimization
1) The Effect of Limited Network Bandwidth and its Utilization
      by Latency Hiding Techniques in Large-scale Shared Memory Systems;
      Sunil Kim and Alexander V. Veidenbaum;
      IBM and University of Illinois at Chicago.
2) Efficient Personalized Communication on Wormhole Networks;
      Fabrizio Petrini and Marco Vanneschi;
      Universita di Pisa.
3) Empirical Evaluation of Deterministic and Adaptive Routing
      with Constant-Area Routers;
      Dianne Miller and Walid Najjar;
      Colorado State University.
1500 - 1530 - Break
1530 - 1700 - Session III. ILP Optimization/Code Scheduling
1) A Register Pressure Sensitive Instruction Scheduler
      for Dynamic Issue Processors;
      Raul E. Silvera, Jian Wang, R. Govindarajan, and Guang R. Gao;
      McGill University.
2) A Parallel Algorithm for Compile-Time Scheduling
      of Parallel Programs on Multiprocessors;
      Yu-Kwong Kwok and Ishfaq Ahmad;
      The Hong Kong University of Science and Technology.
3) Path Profile Guided Partial Dead Code Elimation Using Predication;
      Rajiv Gupta, David A. Berson, and Jesse Z. Fang;
      University of Pittsburgh and Intel Corporation.
1730 - 1830 - Session IV. Short Papers Presentations
1) The PROMIS Compiler Prototype;
      Carrie Brownhill, Alexandru Nicolau, Steven Novack,
      and Constantine Polychronopoulos;
      University of California, Irvine and University of Illinois
      at Urbana-Champaign
2) Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue,
      Microprocessor-Based Systems;
      David H. Albonesi and Israel Koren;
      University of Rochester and University of Massachusetts.
3) Parallel Execution of Radix Sort Program using Fine-Grain
      Communication;
      Yuetsu Kodama, Hirofumi Sakane, Koike Hanpei, Mitsuhisa Sato,
      Shuichi Sakai, and Yoshinori Yamaguchi;
      Electrotechnical Laboratory.
4) Interprocedural Array Remapping;
      Michal Cierniak and Wei Li;
      University of Rochester.
5) Design of Heterogenous Multi-processor Embedded Systems:
      Applying Functional Pipelining;
      Ireneusz Karkowski and Henk Corporaal;
      Delft University of Technology.
5) VLIW Across Multiple Superscalar Processors On A Single Chip:
      A Smart Compiler and a Smart Machine;
      Soohong P. Kim, Raymond R. Hoare, and Henry G. Dietz;
      Purdue University.
1830 - 2100 - Reception and Poster Presentations


Thursday, November 14
0800 - 0830 - Continental Breakfast
0830 - 1000 - Keynote Speech II
1000 - 1030 - Break
1030 - 1200 - Session IV. Profiling and Prediction Based Optimizations


1) Path Prediction for High Issue-Rate Processors;
      Kishore N. Menezes, Sumedh W. Sathaye and Thomas M. Conte;
      North Carolina State University.
2) Buffer-Safe Communication Optimization based on Data Flow Analysis
      and Performance Prediction;
      Thomas Fahringer and Eduard Mehofer;
      University of Vienna.
3) MDL: A Language and Compiler for Dynamic Program Instrumentation;
      Jeffrey Hollingsworth, Barton Miller, Marcelo Gonccalves,
      Oscar Naim, Zhichen Xu, and Ling Zheng;
      University of Maryland and University of Wisconsin.
1200 - 1330 - Lunch
1330 - 1500 - Session V. Compilation Issues for Multiprocessors
1) Optimally Synchronizing Loops on Shared Memory Multiprocessors;
      Ramakrishnan Rajamony and Alan Cox;
      Rice University.
2) Two Techniques for Static Array Partitioning
      on Message-Passing Parallel Machines;
      Eric Hung-Yu Tseng and Jean-Luc Gaudiot;
      University of Southern California.
3) Compiler Algorithms for Optimizing Locality and Parallelism
      on Shared and Distributed Memory Machines;
      M. Kandemir, J. Ramanujam, and A. Choudhary;
      Syracuse University;
      Louisiana State University, and Northwestern University.
1500 - 1530 - Break
1530 - 1700 - Session VI. Compiler/Architecture Interaction
                            in Parallelism Exploitation
1) Effective Usage of Vector Registers
      in Advanced Vector Architectures;
      Luis Villa, Roger Espasa, and Mateo Valero;
      Universitat Politecnica de Catalunya-Barcelona.
2) Static Locality Analysis for Cache Management;
      F. Jesus Sanchez, Antonio Gonzalez, and Mateo Valero;
      Universitat Politecnica de Catalunya.
3) Overcoming Limitations of Prefetching in Multiprocessors
      by Compiler-Initiated Coherence Actions;
      Jonas Skeppstedt;
      Chalmers University of Technology.


Friday, November 15
0800 - 0830 - Continental Breakfast
0830 - 1000 - Keynote Speech III
1000 - 1030 - Break
1030 - 1200 - Session VII. High Level Parallelization
1) Towards a Time and Space Efficient Functional Implementation
      of a Monte Carlo Photon Transport Code;
      J.P. Hammes and A.P.W. Bohm;
      Colorado State University.
2) Direct Generation of Data-Driven Program
      for Stream-Oriented Processing;
      Kei Karasawa, Makoto Iwata, and Hiroaki Terada;
      Osaka University and Kochi University of Technology.
3) Determining the Idle Time of a Tiling: New Results;
      Yves Robert, Frederic Desprez, Jack Dongarra and Fabrice Rastello;
      University of Tennessee at Knoxville.


CONFERENCE ORGANIZERS


General Chair: John Feo
Tera Computer Company


Program Chair: Alex Nicolau
UC, Irvine


Tutorial Chair: Andrew Wendelborn
University of Adelaide


Finance Chair: Walid Najjar
Colorado State University


Publicity Chair: Thomas M. DeBoni
Lawrence Berkeley National Laboratory


Arrangements: Judy Michels
Lawrence Livermore National Laboratory


SPONSORS


The International Federation of Information Processing Societies,
Working Group 10.3 for Concurrent Systems.


The Institute of Electrical and Electronic Engineers,
Computer Society.


The Association for Computing Machinery,
Special Interest Group on Computer Architecture.
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