RSIM (Rice Simulator for ILP Multiprocessors) release announcement

We are pleased to announce the release of RSIM - Rice Simulator for ILP
Multiprocessors - version 1.0.


RSIM simulates shared-memory multiprocessors (and uniprocessors) built from
processors that aggressively exploit instruction-level parallelism (ILP).
RSIM is execution-driven and models state-of-the-art ILP processors, an
aggressive memory system, and a multiprocessor coherence protocol and
interconnect, including contention at all resources. Key features include:


Processor simulation features:
o Multiple instruction issue
o Out-of-order scheduling
o Register renaming
o Static and dynamic branch prediction
o Non-blocking loads and stores
o Speculative load execution before prior stores disambiguated
o Optimized memory consistency model implementations


Memory simulation features:
o Two-level cache hierarchy
o Multiported and pipelined L1 cache, pipelined L2 cache
o Multiple outstanding cache requests
o Memory interleaving
o Software-controlled non-binding prefetching


Multiprocessor system features:
o CC-NUMA shared-memory system with directory-based coherence
o Support for MSI or MESI cache coherence protocols
o Support for sequential consistency, processor
         consistency, and release consistency
o Wormhole-routed mesh network




More information is available at http://www-ece.rice.edu/~rsim/dist.html .




Vijay S. Pai
Parthasarathy Ranganathan
Sarita V. Adve


Dept. of Electrical and Computer Engineering
Rice University
rsim@rice.edu
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