Call For Participation, ICPP '97

26th INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING
August 11-15, 1997
http://yake.ecn.purdue.edu/~icpp/


********************************************************************
                Advance registration deadline is August 1, 1997
********************************************************************


The International Conference on Parallel Processing (ICPP97) enters
its second quarter century August 11-15, 1997 at the Indian Lakes
Resort in Bloomingdale, IL. Parallel processing is a field evolving;
ICPP97 is helping by focusing on the newest and best research in
architecture & networking, software, and algorithms & applications.


The ICPP97 conference features a keynote address by Thomas Sterling,
four panels, and three-track parallel-session presentations of 74
top-quality papers selected by full peer and program committee review
(the regular paper acceptance rate was less than 19%). All accepted
papers appear in an archival proceedings published by the IEEE
Computer Society Press. This 26th ICPP conference also continues the
tradition of providing a very friendly environment for parallel
processing researchers to meet and interact, including an informal
open-bar gathering each night.


The three-day conference is preceded by a day of tutorials, and is
followed by a one-day workshop on "Putting Parallelism to Work:
Parallel Applications in Production" (which also has a hardcopy
proceedings).


ICPP97 will be held at the Indian Lakes Resort in Bloomingdale, IL
(about 15 miles west of the Chicago O'Hare International Airport). This
resort has a variety of sports facilities, including two 18-hole golf
courses. Regular limousine service is available between the hotel and
the O'Hare International Airport (or Midway Airport).


The following sections of this text contain the complete CONFERENCE
PROGRAM, WORKSHOP PROGRAM, TUTORIALS, and REGISTRATION/RESERVATION
INFORMATION. More complete information about ICPP97 is available
on-line at: http://yake.ecn.purdue.edu/~icpp/
========================================================================


ICPP97 PRELIMINARY CONFERENCE SCHEDULE
Tuesday-Thursday, August 12-14, 1997


The complete listing of papers for each session is attached.
In the complete listing, each paper is described by "(R)" for
Regular length or "(C)" for Concise length, then the full title of the
paper, and finally a "-" followed by the author name(s).


------------------------------------------------------------------------


Keynote: 10:00-11:00, Tuesday, August 12, 1997


Speaker: Thomas Sterling


Title: Parallel Computing at the Point of Inflection


Abstract: Parallel computing system development is facing extreme challenges
>from the success of advanced microprocessor technology, market forces,
inadequate system software, high costs, entrenched methodologies, and the
end of the Cold War. A once energetic and thriving research community is
perceived to be in retrenchment seeking the will and the way while exciting
opportunities in networking and webware attract an increasing proportion of
research budgets and talent. High placed sources on both sides of the
funding cycle question even the very existence of fresh and innovative ideas
in parallel computing. In fact, the opposite is true and this keynote
presentation will demonstrate that parallel processing is preparing for
rapid new advances while shedding the burden of flawed conventional thinking
that has proven a barrier in recent years. Citing examples from his own work
in the Beowulf class of "Piles of PCs", Petaflops computer design,
distributed shared memory performance benchmarking, multithreaded
architecture, and the new concept of Continuum Computer architecture the
speaker will identify the critical factors driving the new wave in parallel
processing and present a framework for a parallel processing community
research agenda into the 21st century.
------------------------------------------------------------------------


Session 1A/B/C: 1:00-2:30, Tuesday, August 12, 1997


Session 1A: Parallel Algorithms


(R) Optimal Sorting Algorithms on Incomplete Meshes with Arbitrary
Fault Patterns - Behrooz Parhami and Chi-Hsiang Yeh
(C) Broadcast-Efficient Sorting in the Presence of Few Channels - Koji
Nakano, Stephan Olariu, and James L. Schwing
(C) Efficient Parallel Algorithms for Optimally Locating a k-Leaf Tree
in a Tree Network - Biing-Feng Wang, Shan-Chyun Ku, and Wei-Kuan Shih
Network
(C) Efficient Parallel Algorithms on Distance-Hereditary Graphs -
Sun-Yuan Hsieh, Gen-Huey Chen, Chin-Wen Ho, Tsan-sheng Hsu, and
Ming-Tat Ko


Session 1B: Network Modeling


(R) Multidimensional Network Performance with Unidirectional Links -
James R. Anderson and Seth Abraham
(R) Network Performance under Physical Constraints - Fabrizio Petrini
and Marco Vanneschi
(C) An Improved Analytical Model for Wormhole Routed Networks with
Application to Butterfly Fat-Trees - Ronald I. Greenberg and Lee Guan
(C) Performance and Implementation Aspects of Higher Order Head-of-Line
Blocking Switch Boxes - Michael Jurczyk


Session 1C: Compilers I - Data Layout And Access


(R) Data Distribution Analysis and Optimization for Pointer-Based
Distributed Programs - Jenq Kuen Lee, Dan Ho, and Yue-Chee Chuang
(R) Automatic Partitioning of Data and Computations on Scalable Shared
Memory Multiprocessors - Sudarsan Tandri and Tarek S. Abdelrahman
(C) Compiler Techniques for Effective Communication on
Distributed-Memory Multiprocessors - Angeles G. Navarro, Yunheung
Paek, Emilio L. Zapata, and David Padua
(C) Combining Loop Fusion with Prefetching on Shared-memory
Multiprocessors - Naraig Manjikian
------------------------------------------------------------------------


Session 2A/B/C: 3:00-4:30, Tuesday, August 12, 1997


Session 2A: Embeddings and Routings


(R) Efficient Multicast Algorithms in All-port Wormhole Routed
Hypercubes - Vivek Halwan and Füsun Özgüner
(C) A Class of Fixed-Degree Cayley-Graph Interconnection Networks
Derived by Pruning k-ary n-cubes - Behrooz Parhami and Ding-Ming Kwai
(C) Embedding of Binomial Trees in Hypercube Multiprocessors with Link
Faults - Jie Wu, Eduardo B. Fernandez, and Yinqiu Luo
(C) An Optimal Multiple Bus Network for Fan-in Algorithms -
Ramachandran Vaidyanathan and Hettihe P. Dharmasena


Session 2B: Parallelism Management


(R) Multiscalar Execution along a Single Control Flow - Krishna K.
Sundararaman and Manoj Franklin
(C) Efficient Processor Allocation Scheme for Multi-Dimensional
Interconnection Networks - Hyunseung Choo
(C) An Integrated Processor Management Scheme for the Mesh Connected
Multicomputer Systems - Chung-yen Chang and Prasant Mohapatra
(C) Quantitative Analysis on Caching Effect of I-Structure Data in
Frame-Based multithreaded Processing - Hyonk-Shik Kim, Soonhoi Ha, and
Chu Shik Jhon


Session 2C: IO and Data Structures in Distributed Systems


(R) Improving the Performance of Out-of-Core Computations - Mahmut
Kandemir, J. Ramanujam, and Alok Choudhary
(R) A Framework For Parallel Tree-Based Scientific Simulations -
Pangfeng Liu and Jan-Jan Wu
(C) Fault-Tolerant Parallel Applications Using Queues and Actions - Jim
Smith
(C) Message Encoding Techniques for Efficient Array Redistribution -
Yeh-Ching Chung and Ching-Sheng Sheu
------------------------------------------------------------------------


Panel 1: 7:00-8:30, Tuesday, August 12, 1997


Wide-Spread Acceptance Of General-Purpose Large-Scale Parallel
Machines: Fact, Future, Or Fantasy?


Moderator and organizer: H. J. Siegel


Panelists: H. J. Siegel, Purdue University; Bruce H. Alper, Cambridge
Parallel Processing; Vipin Kumar, University of Minnesota; Richard
Linderman, Rome Laboratory; Dan Marinescu, Purdue University; John D.
McCalpin, Silicon Graphics, Inc.; and Michael Wolfe, The Portland
Group, Inc.
------------------------------------------------------------------------


Session 3A/B/C: 9:30-11:00, Wednesday, August 13, 1997


Session 3A: Scheduling I - Algorithms


(R) A Parametrized Branch-and-Bound Strategy for Scheduling of
Precedence-Constrained Tasks on a Multiprocessor System - Jan Jonsson
and Kang G. Shin
(C) Real-Time Job Scheduling in Hypercube Systems - O-Hoon Kwon, Jong
Kim, SungJe Hong, and Sunggu Lee
(C) Hindsight Helps: Deterministic Task Scheduling with Backtracking -
Yueh-O Wang, Nancy M. Amato, and D. K. Friesen
(C) Improving DAG Scheduling by Local Compaction - Min-You Wu, Wei
Shu, and Jun Gu


Session 3B: Wormhole Networks


(R) An Efficient Deadlock Recovery Technique for True Fully Adaptive
Routing in Wormhole Networks - J.M. Martinez, P. Lopez, J. Duato, and
T.M. Pinkston
(R) Turn Grouping for Efficient Barrier Synchronization in
Wormhole-Routed Mesh Networks - Kuo-Pao Fan and Chung-Ta King
(C) Throttle and Preempt: A New Flow Control for Real-Time
Communications in Wormhole Networks - Hyojeong Song, Boseob Kwon, and
Hyunsoo Yoon
(C) Tree-Based Multicasting on Wormhole Routed Multistage
Interconnection Networks - Vara Varavithya and Prasant Mohapatra


Session 3C: Consistency and Communication


(R) The Affinity Entry Consistency Protocol - Cristiana Seidel, Ricardo
Bianchini, and Claudio Amorim
(C) Quantifying the Effects of Communication Optimizations - Sung-Eun
Choi and Lawrence Snyder
(C) Reducing Overheads of Local Communications in Fine-Grain Parallel
Computation - Jin-Soo Kim, Soonhoi Ha, and Chu Shik Jhon
(C) Parallel Synchronization of Continuous Time Discrete Event
Simulators - Peter Frey, Harold W. Carter, and Philip A. Wilsey
------------------------------------------------------------------------


Session 4A/B/C: 1:00-2:30, Wednesday, August 13, 1997


Session 4A: Data Distribution


(R) Efficient Algorithms for Multi-dimensional Block-Cyclic
Redistribution of Arrays - Viktor K. Prasanna and Young Won Lim
(C) Effects of Dynamic Task Distributions on the Performance of a
Class of Irregular Computations - Hemal V. Shah and Jose A. B. Fortes


Session 4B: Memory Organizations


(R) Hardware vs. Software Implementation of COMA: A Performance
Comparison - Adrian Moga, Alain Gefflaut, and Michel Dubois
(R) Performance and Configuration of Hierarchical Ring Networks for
Multiprocessors - V. Carl Hamacher and Hong Jiang
(C) An Effective Memory-Processor Integrated Architecture for Computer
Vision - Youngsik Kim, Tack-Don Han, Shin-Dug Kim, and Sung-Bong Yang


Session 4C: Load Balancing And Scheduling


(R) Load Balancing and Work Load Minimization of Overlapping Parallel
Tasks - Prithviraj Banerjee, Gagan Hasteer, and Venkatram Krishnaswamy
(R) A Good Processor Management Scheme = Fast Allocation + Efficient
Scheduling - Byung S. Yoo and Chita R. Das
(C) Automatic Parallelization and Scheduling of Programs on
Multiprocessors using CASCH - Ishfaq Ahmad, Yu-Kwong Kwok, Min-You Wu,
and Wei Shu
(C) Probabilistic Rotation: Scheduling Graphs with Uncertain Execution
Time - Edwin Hsing-Mean Sha, Sissades Tongsima, Chantana
Chantrapornchai, and Nelson Passos
------------------------------------------------------------------------


Session 5A/B/C: 3:00-4:30, Wednesday, August 13, 1997


Session 5A: Prefetching In Multiprocessors


(R) Hybrid Compiler/Hardware Prefetching for Multiprocessors Using
Low-Overhead Cache Miss Traps - Jonas Skeppstedt and Michel Dubois
(R) An Adaptive Sequential Prefetching Scheme in Shared-Memory
Multiprocessors - Myoung Hyunsoo Yoon, Kwon Tcheun, and Seung Ryoul
Maeng
(R) Stride-directed Prefetching for Secondary Caches - Sunil Kim and
Alexander Veidenbaum


Session 5B: Local Area And Wireless Networks


(R) Design of Scalable and Multicast Capable Cut-Through Switches for
High-Speed LANs - Mingyao Yang and Lionel M. Ni
(R) Real-time Multicast in Wireless Communication - Sourav
Bhattacharya, Laila Nahar, and Sandeepan Sanyal


Session 5C: Fault-Tolerant Networks


(R) Performance Evaluation of Fault-Tolerance for Parallel
Applications in Networked Environments - Pierre Sens and Bertil Folliot
(C) Design of a Circuit-Switched Highly Fault-Tolerant k-ary n-cube -
Baback A. Izadi and Füsun Özgüner
(C) Design and Analysis of a Fault-Tolerant Modular Architecture for
Star Networks - Chungti Liang, Sourav Bhattacharya, and Jack Tan
(C) On the Multiple Fault Diagnosis of Multistage Interconnection
Networks: The Lower Bound and the CMOS Fault Model - Fabrizio
Lombardi, X.T. Chen, Y.-N. Shen, and S. Horiguchi
------------------------------------------------------------------------


Panel 2: 7:00-8:30, Wednesday, August 13, 1997


In Search of the "Killer Application"


Moderator and organizer: M. T. O'Keefe
------------------------------------------------------------------------


Panel 3: 9:30-11:00, Thursday, August 14, 1997


Of Languages and Libraries


Moderator and organizer: David Padua
------------------------------------------------------------------------


Session 6A/B/C: 1:00-2:30, Thursday, August 14, 1997


Session 6A: Load Balancing


(R) Adaptive Load Balancing Algorithms Using Symmetric Broadcast
Networks: Performance Study on an SP2 - Sajal K. Das, Daniel J.
Harvey, and Rupak Biswas
(R) D-LBSB: A Distributed Load Balancing Algorithm for Channel
Assignment in Cellular Mobile Networks - Sajal K. Das, Sanjoy K. Sen,
and Rajeev Jayaram


Session 6B: Multicast Communication


(R) Optimal Multicast with Packetization and Network Interface Support
- Ram Kesavan and Dhabaleswar K. Panda
(R) An Euler Path Based Technique for Deadlock-free Multicasting -
Nidhi Agrawal and C. P. Ravikumar
(C) Performance Analysis and Simulation of Multicast Networks -
Yuanyuan Yang and Jianchao Wang
(C) Sufficient Conditions for Optimal Multicast Communication - Barbara
Birchler, Abdol-Hossein Esfahanian, and Eric Torng


Session 6C: Compilers II - Analysis, Allocation, And Mapping


(R) False Sharing Elimination by Selection of Runtime Scheduling
Parameters - Jyh-Herng Chow and Vivek Sarkar
(R) A Register Allocation Technique Using Register Existence Graph -
Akira Koseki, Hideaki Komatsu, and Yoshiaki Fukazawa
(C) Precise Call Graph Construction for OO Programs in the Presence of
Virtual Functions - Deepankar Bairagi, Sandeep Kumar, and Dharma P.
Agrawal
(C) Automatic Generation of Injective Modular Mappings - Hyuk-Jae Lee
and Jose A.B. Fortes
------------------------------------------------------------------------


Session 7A/B/C: 3:00-4:30, Thursday, August 14, 1997


Session 7A: Applications


(R) Implementations of a Feature-Based Visual Tracking Algorithm on
Two MIMD Machines - Mark B. Kulaczewski and Howard Jay Siegel
(R) Background Compensation and an Active-Camera Motion Tracking
Algorithm - Rohit Gupta, Mitchell D. Theys, and H. J. Siegel
(C) Exploiting Task and Data Parallelism in Parallel Hough and Radon
Transforms - Prithviraj Banerjee and Dilip Krishnaswamy


Session 7B: Communication And Synchronization Issues


(R) Communication in Parallel Applications: Characterization and
Sensitivity Analysis - Dale Seed, Anand Sivasubramaniam, and Chita Das
(R) How Much Does Network Contention Affect Distributed Shared Memory
Performance? - Donglai Dai and Dhabaleswar K. Panda
(R) The Implementation of Low Latency Communication Primitives in the
Snow Prototype - Kanad Ghose, Seth Melnick, Tom Gaska, Seth Goldberg,
Arun K. Jayendran, and Brian T. Stein


Session 7C: Scheduling II - Software


(R) Decisive Path Scheduling: A New List Scheduling Method - Gyung-Leen
Park, Behrooz Shirazi, and Jeff Marquis
(R) Modeling The Impact of Run-Time Uncertainty on Optimal Computation
Scheduling Using Feedback - Richard Dietz, Thomas Casavant, Todd
Scheetz, Terry Braun, and Mark Andersland
(C) Trace-driven Analysis of Migration-based Gang-Scheduling Policies
for Parallel Computers - Sanjeev Setia
(C) A Global Computing Environment for Networked Resources - Haluk
Topcuoglu and Salim Hariri
------------------------------------------------------------------------


Panel 4: 7:00-8:30, Thursday, August 14, 1997


COTS Parallel Processing: Are We There Yet?


Moderator and organizer: Hank Dietz
========================================================================


ICPP97 PRELIMINARY WORKSHOP SCHEDULE
Friday, August 15, 1997


"PUTTING PARALLELISM TO WORK: PARALLEL APPLICATIONS IN PRODUCTION"


The goal of this workshop is to determine the current state-of-the-art
in parallel applications. Note that this includes applications that
apply multiple processors to a single task as well as those that
execute many loosely-coupled tasks to increase throughput. Within the
context of parallel applications issues in programming models, mass
storage, parallel machine architectures (cluster, SMP, DSM), and
visualization will be discussed.


The workshop will present applications from a variety of areas,
including traditional applications in weather forecasting, ocean
circulation simulation and electromagnetics, and newer commerical
applications, including parallel relational databases, crash dynamics,
and entertainment and visualization. The application developers
presenting at this workshop will focus on the following issues:


      * parallel structure of the applications
      * software and parallel programming techniques necessary to exploit
          that structure
      * hardware platforms: past, present, future
      * future parallel computational and storage requirements
      * future plans for using parallelism to meet high-end computing needs


For traditional researchers in parallel processing this workshop will
provide an interesting look at the current state-of-the-art in parallel
applications and will hopefully provide them with useful insights on
what problems are yet to be addressed by the traditional parallel
processing research community.


------------------------------------------------------------------------
The current schedule is as follows:


8:00-9:00am


Refreshments and Workshop Signup


------------------------------------------------------------------------
9:00-10:30am


Applying Parallelism to Environmental Prediction


Aaron Sawdey, University of Minnesota and SGI/Cray, Eagan, MN


Tom Rosmond, Naval Research Laboratory, Monterey, CA


------------------------------------------------------------------------
10:30-10:45am
Break


------------------------------------------------------------------------
10:45-12:00pm


Multiprocessor and Parallel Storage Systems for Commercial Databases,
Volume Visualization and Smooth Motion Animation


Mark Coyle, Parallel Database and Cluster Development, Oracle Corp,
Redwood Shores, CA


Thomas Ruwart, Laboratory for Computational Science and Engineering, U.
Minnesota, Minneapolis, MN


------------------------------------------------------------------------
12:00-12:30pm


Panel Session on Future Performance and Storage (Disk and Main Memory)
Capacity Requirements for Parallel Systems


------------------------------------------------------------------------
12:30-2:00pm
Lunch (on your own)


------------------------------------------------------------------------
2:00-2:45pm


Parallel Application and Mass Storage Issues in Entertainment


Kevin Mullican, RFX Inc., Hollywood, CA


------------------------------------------------------------------------
2:45-3:30pm


Parallel Processing for Automobile Crash Dynamics


Dave Strenski, SGI/Cray Research


------------------------------------------------------------------------
3:30-3:45pm
Break


------------------------------------------------------------------------
3:45-4:30pm


Exploiting Parallelism for Computational Electromagnetics


Allen Taflove, Northwestern University, Evanston, IL


------------------------------------------------------------------------
4:30-5:00pm


Panel Session on Current and Future Programming Models for Parallel
Applications
========================================================================


ICPP97 PRELIMINARY TUTORIAL SCHEDULE
Monday, August 11, 1997


There are three full-day tutorials scheduled for Monday, August 11,
1997. Registration for the tutorials is independent of registration
for the conference and workshop.


You can register for a tutorial up to the day of the tutorials.
However, there might not be space for you if you register late.
Conversely, if early registration is low, a tutorial may be cancelled
(we will note any such cancellation here). There is also a discount
for tutorial registration before July 25, 1997; student registration
is $180 instead of $200, and regular registration is $250 instead of
$300. In summary, register early!


The following table summarizes the complete preliminary tutorial
schedule.


                                                                Monday, August 11, 1997
    8:00-8:30 Tutorial Registration
                        Tutorial 1 Tutorial 3
                        Parallelism in Tutorial 2 Parallel
  8:30-10:00 Media-Processing: Concurrent Object Algorithms for
                        Architectural and Design Oriented VLSI CAD
                        Implications Programming Applications
  10:00-10:30 Break


  10:30-12:00Tutorial 1 Tutorial 2 Tutorial 3
                        Continued.... Continued.... Continued....
  12:00-1:30 Lunch


    1:30-3:00 Tutorial 1 Tutorial 2 Tutorial 3
                        Continued.... Continued.... Continued....
    3:00-3:30 Break


    3:30-5:00 Tutorial 1 Tutorial 2 Tutorial 3
                        Continued.... Continued.... Continued....
------------------------------------------------------------------------


Tutorial 1: Monday, August 11, 1997


                                            Parallelism in Media-Processing:
                                      Architectural and Design Implications


                                                              Pradeep Dubey
                                                          IBM, T. J. Watson


Audience: Professionals seeking a technical overview of
mediaprocessing and its implications, computer architects, designers,
and multimedia software developers.


Course Description: The recent surge of interest in programmable
mediaprocessing is unprecedented. It has the potential of radically
altering the nature and needs of "general-purpose" processing. This
tutorial will explain the basics of programmable mediaprocessing from
the point of view of a processor architect and designer. A brief
description of various emerging/projected multimedia scenarios will be
followed by a detailed discussion of various architectural and design
implications. We will conclude with performance analysis of selected
kernels, tasks, and scenarios. Discussion of these topics will include
comparative examples from various mediaprocessing platforms, including
SPARC/VIS, Intel/MMX, PA-RISC/MAX MIPS/MDMX, Chromatics/Mpact,
Philips/Trimedia, and MicroUnity. The information will solely be based
on published reports of these platforms.


Instructor Bio: Pradeep K. Dubey is a Research Staff Member at the
IBM T.J. Watson Research Center. Prior to joining IBM in 1991, he
worked at Intel Corporation. Both at IBM and Intel, he has worked on
design, architecture, and performance modeling issues of various
microprocessors. At Intel he was a member of the 80386, 80486, and the
Pentium architecture teams. At IBM he is currently working on research
issues related to general purpose processors based on multiple
speculative control flows and special purpose processors aimed at
emerging multimedia applications. He has published extensively and
filed several patents in the area of computer architecture. He is also
a Senior Member of IEEE.
------------------------------------------------------------------------


Tutorial 2: Monday, August 11, 1997


                                      Concurrent Object Oriented Programming


                                                                    Gul Agha
                                  University of Illinois at Urbana-Champaign


Audience: The tutorial will be beneficial to individuals doing
research and development of distributed or parallel software.
Specifically, they may be involved in software development for
distributed applications, embedded systems, or high-performance
computing. Attendees should know the basics of object-oriented
programming and concurrency, for example, by having taken standard
courses in programming languages and operating systems.


Course Description: The tutorial will provide an understanding of the
state of the art in distributed computing. It will briefly introduce
Actors, a formal model of concurrent computation, and use it to
describe problems of nondeterminism, synchronization, and
coordination. It will then discuss some programming constructs which
simplify programming, namely, concurrent objects, synchronization
constraints, different types of communication, and continuations. More
advanced topics covered will include implementation techniques for
building libraries, compilers and runtime systems. Finally, recent
progress in supporting software composition using software bus, object
brokers, meta-architectures, etc., will be described. Examples from a
number of domains, such as fault-tolerant computing, real-time systems,
multi-agent systems, and mobile computing, will be used to illustrate
the ideas.


Instructor Bio: Gul Agha is Director of the Open Systems Laboratory
at the University of Illinois at Urbana-Champaign and an Associate
Professor in the Department of Computer Science. His is the author of
a widely cited book, "Actors: A Model of Concurrent Computing in
Distributed Systems," (MIT Press, 1986) and co-editor of "Research
Directions in Concurrent Object Oriented Programming" (MIT Press,
1993). Dr. Agha is an ACM International Lecturer, Editor-in-Chief of
"IEEE Parallel and Distributed Technology," and Associate Editor of
"Theory and Practice of Object Systems" (John Wiley).
------------------------------------------------------------------------


Tutorial 3: Monday, August 11, 1997


                              Parallel Algorithms for VLSI CAD Applications


                                                              Prith Banerjee
                                                    Northwestern University


Audience: The tutorial will be of value to parallel processing users
who are interested about the rapidly changing field of computational
requirements in the VLSI CAD. This tutorial will also be of value to
CAD developers and users in the next few years if they wish to
efficiently use the technology of parallel processing to solve the
problems of the future. Finally, the tutorial will be of immense value
to researchers in the parallel processing community who are constantly
looking for interesting problems to be solved.


Course Description: This tutorial will discuss the use of parallel
processing for solving problems in a growing application area whose
computational requirements are enormous: VLSI computer-aided design
applications. We will describe practical, parallel algorithms that are
suitable for shared memory MIMD, message passing MIMD, and SIMD
parallel machines. For each of the CAD tasks, the sequential
algorithm for solving the problem will first be presented. Then the
different approaches to exploiting parallelism in the problem will be
discussed and critiqued. Next, parallel algorithms for specific
approaches for parallelism on SIMD, shared memory MIMD, and
distributed memory MIMD programming models will be presented. Results
of case studies of real speedups obtained on real parallel machines on
benchmark circuits will be described.


Instructor Bio: Prith Banerjee is currently the Walter P. Murphy
Chaired Professor of Electrical and Computer Engineering and Director
of the Center for Parallel and Distributed Computing. at Northwestern
University in Evanston, Illinois. Prior to that he was the Director
of the Computational Science and Engineering program, and Professor of
Electrical and Computer Engineering and the Coordinated Science
Laboratory at the University of Illinois at Urbana-Champaign. Dr.
Banerjee's research interests are in Parallel Algorithms for VLSI
Design Automation, Distributed Memory Parallel Compilers, and Parallel
Architectures with an emphasis on Fault Tolerance, and is the author
of over 180 papers in these areas.
========================================================================


REGISTRATION/RESERVATION INFORMATION


A registration form is at: http://yake.ecn.purdue.edu/regform.html
Alternatively, you can fill-out the following text-based form.


Name (for badge and attendee list):


Affiliation (for badge and attendee list):


Email address (for attendee list):


Home page URL (for attendee list):


Full conventional mail (postal) address:










Daytime (work) phone number:


Fax number:


Are You A Full-Time Student (ID Required)? [] Yes [] No


ICPP97 consists of one day of tutorials, three days of conference, and
then one day of workshop. You can register for each separately,
although there is a discount for attending both conference and
workshop. The registration fees are:


                                            Before August 1, 1997 After August 1, 1997
                                            Regular Student Regular Student
Tutorial 1, 2, or 3 $250 $180 $300 $200
Conference $375 $200 $450 $250
Workshop $150 $100 $170 $120
Conference + Workshop $425 $225 $500 $275


Since the tutorials run concurrently, you can attend at most one
tutorial. Mark what you wish to attend:


[] Tutorial 1, Monday, August 11, 1997:
      Parallelism in Media-Processing: Architectural and Design Implications
[] Tutorial 2, Monday, August 11, 1997:
      Concurrent Object Oriented Programming
[] Tutorial 3, Monday, August 11, 1997:
      Parallel Algorithms for VLSI CAD Applications
[] Conference, Tuesday-Thursday, August 12-14, 1997
      (includes hardcopy conference proceedings, lunches and evening parties)
[] Workshop, Friday, August 15, 1997
      (includes hardcopy workshop proceedings and lunch)


Your total registration fees are:


Write your US bank check for the full amount, payable to ICPP. Mail
your check and registration info to:


Professor Mike Liu
Department of Computer and Information Science
2015 Neil Avenue
The Ohio State University
Columbus, OH, 43201-1277, USA
Phone: (614) 292 6552




For hotel reservations, YOU DIRECTLY CONTACT THE HOTEL. The hotel rate
is $106/night for up to two people sharing a room; a limited supply of
rooms for up to two students are available for $70/night. Contact the
hotel to reserve your room by August 1, 1997. (Note: the hotel's area
code recently changed from 708 to 630.)


Indian Lakes Resort
250 West Schick Road
Bloomingdale, IL 60108
Phone: (630) 529 0200
FAX: (630) 529 0675
--

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