Advance Program for 24th Annual ISCA Conference (ISCA '97)

                                                                ADVANCE PROGRAM


                          The 24th Annual IEEE/ACM International Symposium on
                                                          COMPUTER ARCHITECTURE


                                                              Denver, Colorado
                                                                June 2-4, 1997


                                    Sponsored by IEEE TC-MICRO and ACM SIGMICRO


_______________________________________________________________________________


This message contains the Advance Program for the 24th Annual IEEE/ACM Interna-
tional Symposium on Computer Architecture (ISCA '97). This and a wealth of
other conference information (including pointers to the home pages of all auth-
ers with papers that will appear in the proceedings) can be accessed via:


World Wide Web at http://arch.cs.ucdavis.edu/ISCA97
or by anonymous ftp from american.cs.ucdavis.edu:/ISCA97
or by sending e-mail to isca97@boulder.colorado.edu


*******************************************************************************


CONFERENCE AT A GLANCE


Sunday, June 1
---------------


08:30-12:30 Tutorial T1: Arch. and Design Implications of Mediaprocessing
08:30-12:30 Tutorial T2: Parallel Processing Architectures Using PCs and Linux
13:30-17:30 Tutorial T3: Compiling and Executing Multiple Superscalar Threads
13:30-17:30 Tutorial T4: System Issues in Designing Parallel I/O Subsystems
08:30-17:30 Workshop W1: Performance Analysis and its Impact on Design
08:30-17:30 Workshop W2: Mixing Logic and DRAM: Chips that Compute and Remember


18:30-20:00 Welcoming Reception


Monday, June 2
---------------


09:00-09:30 Welcoming Remarks
09:30-10:30 Keynote Address: James E. Smith, Univ. of Wisconsin-Madison
11:00-12:30 Session 1a: Caching Techniques for ILP
11:00-12:30 Session 1b: Networks and Input/Output
12:30-14:00 Lunch - on your own
14:00-15:30 Session 2: Multiprocessors
16:00-17:30 Session 3: Memory System Design


21:00- Business Meeting


Tuesday, June 3
---------------


09:00-10:30 Session 4: Issues in Shared Memory Systems
11:00-12:30 Session 5a: Improving ILP
11:00-12:30 Session 5b: NUMA and COMA Architectures
12:30-14:00 Eckert-Mauchly Award Luncheon
14:00-15:30 Session 6: Prefetching and Prediction


15:30- Excursion


Wednesday, June 4
---------------


09:00-10:30 Session 7: Branch Prediction
11:00-12:30 Session 8: Managing the Memory Hierarchy and Memory Centric Archs


12:30- End of ISCA'97 Conference


*******************************************************************************


CONFERENCE IN DETAIL


Sunday, June 1
---------------


8:30-12:30 Tutorial T1:
                        "Architectural and Design Implications of Mediaprocessing"


    Speaker: Pradeep K. Dubey, IBM, T.J. Watson Research Center
_______________________________________________________________________________


8:30-12:30 Tutorial T2:
                        "Parallel Processing Architectures Using PCs and Linux"


    Speaker: Hank Dietz, Purdue University
_______________________________________________________________________________


13:30-17:30 Tutorial T3:
                          "Compiling and Executing Multiple Superscalar Threads"


    Speakers: Alex Nicolau, University of California, Irvine and
                        Constantine D. Polychronopoulos, University of Illinois
_______________________________________________________________________________


13:30-17:30 Tutorial:
                          "T4 System Issues in Designing Parallel I/O Subsystems"


    Speakers: Rajesh Bordawekar, California Institute of Technology and
                        Alok Choudhary, Northwestern University
_______________________________________________________________________________


8:30-17:30 Workshop W1:
                        "Performance Analysis and its Impact on Design (PAID'97)"


    Organizers: Tom Conte, North Carolina State University and
                            Pradip Bose, IBM T. J. Watson Research Center
_______________________________________________________________________________


8:30-17:30 Workshop W2:
                        "Mixing Logic and DRAM: Chips that Compute and Remember"


    Organizers: David A. Patterson University of California, Berkeley and
                            Michael D. Smith, Harvard University
_______________________________________________________________________________


18:30-20:00 Welcoming Reception


===============================================================================


Monday, June 2
---------------


09:00-09:30 Welcoming Remarks:
                                    Andrew Pleszkun, General Chair
                                    Trevor Mudge, Program Chair


09:30-10:30 Keynote Address: "Amdahl's Law: Not Just an Equation"
                                    James E. Smith, Professor, University of Wisconsin-Madison
_______________________________________________________________________________


11:00-12:30 Session 1a: Caching Techniques for Instruction Level Parallelism
                          (Concurrent with Session 1b)


                          Session Chair: Tom Conte, North Carolina State University


+ "Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic
      Code Sequences," Sriram Vajapeyam and Tulika Mitra, Dept. of Computer Sci-
      ence and Automation - Indian Institute of Science.


+ "Exploiting Instruction Level Parallelism in Processors by Caching Scheduled
      Groups," Ravi Nair and Martin E. Hopkins, IBM T.J. Watson Research Center.


+ "DAISY: Dynamic Compilation for 100% Architectural Compatibility," Erik Alt-
      man and Kemal Ebcioglu, IBM T.J. Watson Research Center.


_______________________________________________________________________________


11:00-12:30 Session 1b: Networks and Input/Output
                          (Concurrent with Session 1a)


                          Session Chair: Peter Chen, The University of Michigan


+ "On Deadlocks in Interconnection Networks," Timothy Mark Pinkston and Sugath
      Warnakulasuriya," University of Southern California.


+ "Implementing Multidestination Worms in Switch-Based Parallel Systems:
      Architectural Alternatives and their Impact," Craig B. Stunkel, IBM T. J.
      Watson Research Center, Rajeev Sivaram and Dhabaleswar K. Panda, The Ohio
      State University.


+ "Tolerating Multiple Failures in RAID Architectures with Optimal Storage and
      Uniform Declustering," Guillermo A. Alvarez, Walter A. Burkhard and Flaviu
      Cristian Dept. of Computer Science and Engineering, University of Califor-
      nia, San Diego.


_______________________________________________________________________________


14:00-15:30 Session 2: Multiprocessors


                          Session Chair: David Wood, University of Wisconsin-Madison


+ "Hardware Fault Containment in Scalable Shared-Memory Multiprocessors," Dan
      Teodosiu, Joel Baxter, Kinshuk Govil, John Chapin*, Mendel Rosenblum and
      Mark Horowitz, Computer Systems Laboratory Stanford University, * MIT
      Laboratory for Computer Science.


+ "Effects of Communication Latency, Overhead and Bandwidth in a Cluster
      Architecture," Richard P. Martin, Amin M. Vahdat, David E. Culler and Thomas
      E. Anderson, University of California-Berkeley.


+ "The Mercury Interconnect Architecture: A Cost-effective Infrastructure for
      High-performance Servers Wolf-Dietrich Weber," Stephen Gold, Pat Helland,
      Takeshi Shimizu, Thomas Wicki and Winfried Wilcke, HAL Computer Systems.


_______________________________________________________________________________


16:00-17:30 Session 3: Memory System Design


                          Session Chair: Wen-mei Hwu, Univ. of Illinois-Urbana Champaign


+ "The Design and Analysis of a Cache Architecture for Texture Mapping," Ziyad
      Hakura and Anoop Gupta, Stanford University.


+ "Designing High Bandwidth On-Chip Caches," Kenneth Wilson and Kunle Oluko-
      tun, Stanford University.


+ "Memory System Design Considerations in Dynamically-scheduled Processors,"
      Keith I. Farkas, Paul Chow, Norman P. Jouppi*, Zvonko Vranesic, University
      of Toronto, * Digital Equipment Corporation Western Research Lab.


_______________________________________________________________________________


21:00- Business Meeting


===============================================================================


Tuesday, June 3
---------------


09:00-10:30 Session 4: Issues in Shared Memory Systems


                          Session Chair: Timothy Mark Pinkston, Univ. of Southern Califor-
nia


+ "The Interaction of Software Prefetching with ILP Processors in Shared-
      Memory Systems," Parthasarathy Ranganathan, Vijay S. Pai, Hazim Abdel-Shafi
      and Sarita V. Adve, Rice University.


+ "VM-based Shared Memory on Low Latency, Remote Memory Access Networks,"
      Leonidas Kontothanassis*, Galen Hunt, Robert Stets, Nikolaos Hardavellas,
      Michal Cierniak, Srinivasan Parthasarathy, Wagner Meira, Jr., Sandhya Dwar-
      kadas, and Michael L. Scott. Dept. of Computer Science, University Roches-
      ter, * DEC-Cambridge Research Lab.


+ "Efficient Synchronization: Let Them Eat QOLB," Alain Kagi, Doug Burger and
      James R. Goodman, Computer Sciences Department, University of Wisconsin-
      Madison.


_______________________________________________________________________________


11:00-12:30 Session 5a: Improving Instruction Level Parallelism
                          (Concurrent with Session 5b)


                          Session Chair: Dave Patterson, Univ. of California-Berkeley


+ "Dynamic Speculation and Synchronization of Data Dependences," Andreas
      Moshovos, Scott E. Breach, T.N. Vijaykumar and Gurindar S. Sohi, Computer
      Sciences Department, University of Wisconsin-Madison.


+ "Dynamic Instruction Reuse," Avinash Sodani and Gurindar S. Sohi, Computer
      Sciences Department, University of Wisconsin-Madison.


+ "Complexity-Effective Superscalar Processors," Subbarao Palacharla, UW-
      Madison, Norman P. Jouppi, DEC-WRL, J. E. Smith, UW-Madison.


_______________________________________________________________________________


11:00-12:30 Session 5b: NUMA and COMA Architectures
                          (Concurrent with Session 5a)


                          Session Chair: Per Stenstrom, Chalmers University


+ "Coherence Controller Architectures for SMP-based CC-NUMA Multiprocessors,"
      Maged M. Michael, University of Rochester, Ashwini K. Nanda, Beng-Hong Lim,
      IBM T.J. Watson Research Center, and Michael L. Scott, University of
      Rochester.


+ "Reactive NUMA: A Design for Unifying S-COMA and CC-NUMA," Babak Falsafi and
      David A. Wood, Univ. of Wisconsin-Madison.


+ "The SGI Origin 2000: A CC-NUMA Highly Scalable Server," James Laudon and
      Daniel Lenoski, Silicon Graphics.


_______________________________________________________________________________


12:30-14:00 Eckert-Mauchly Award Luncheon


14:00-15:30 Session 6: Prefetching and Prediction


                          Session Chair: Joel Emer, Digital Equipment Corp.


+ "Prefetching Using Markov Predictors," Dirk Grunwald University of Colorado,
      and Douglas Joseph, IBM T.J. Watson Research Center.


+ "Data Prefetching on the HP PA8000," Vatsa Santhanam, Edward H. Gornish and
      Wei-Chung Hsu, Hewlett-Packard.


+ "Target Prediction for Indirect Jumps," Po-Yung Chang, Eric Hao, Yale N.
      Patt, The University of Michigan.


_______________________________________________________________________________


15:30- Excursion


===============================================================================


Wednesday, June 4
---------------


09:00-10:30 Session 7: Branch Prediction


                          Session Chair: David Nagle, Carnegie-Mellon University


+ "The Agree Predictor: A Mechanism for Reducing Negative Branch History
      Interference," Robert Chappell, Eric Sprangle*, Mitch Alsup*, Yale N. Patt,
      Univ. of Michigan, * Ross Technology.


+ "Trading Conflict and Capacity Aliasing in Conditional Branch Predictors,"
      Pierre Michaud (IRISA/INRIA), Andre Seznec (IRISA/INRIA), Richard Uhlig
      (Intel Corporation).


+ "A Language for Describing Predictors and Its Application to Automatic Syn-
      thesis," Joel Emer, DEC, and Nickolas Gloy, Harvard University.


_______________________________________________________________________________


11:00-12:30 Session 8: Managing the Memory Hierarchy and Memory-Centric
                                                  Architectures


                          Session Chair: Michael D. Smith, Harvard University


+ "Run-Time Adaptive Cache Hierarchy Management via Reference Analysis,"
      Teresa L. Johnson and Wen-mei Hwu, Center for Reliable and High-Performance
      Computing, University of Illinois, Urbana-Champaign.


+ "The Energy Efficiency of IRAM Architectures," Richard Fromm, Stylianos Per-
      issakis, Neal Cardwell, Bruce McGaughy, Christoforos Kozyrakis, David
      Patterson, Thomas Anderson and Kathy Yelick, Univ. of California-Berkeley.


+ "DataScalar Architectures," Doug Burger, Stefanos Kaxiras, James R. Good-
      man, Computer Sciences Dept., University of Wisconsin-Madison.


_______________________________________________________________________________


12:30- End of ISCA'97 Conference


*******************************************************************************




Registration Information


Early registration must be received by May 1st, 1997. Full payment in U.S.
dollars must accompany the registration, either by check, or a charge to
MasterCard, Visa or American Express. The registration form with the accom-
panying payment can be mailed to:


        ISCA '97 Registration
        Department of Computer Science
        Campus Box 430
        Boulder, CO 80309-0430


The registration form may also be FAXed if a credit card is being used. The
FAX number is (303) 492-2844. (Email address: isca97@boulder.colorado.edu)


An on-line html registration form is also available at the conference website
(http://arch.cs.ucdavis.edu/ISCA97), along with ascii and postscript versions.
We would greatly appreciate registration via the website form.


Conference registration includes one copy of the proceedings, a ticket for a
reception, the Eckert-Mauchly Award banquet luncheon, a dinner/excursion, and
coffee breaks. Tutorial registration includes tutorial materials and coffee
breaks. The student registration does not include banquets and must be accom-
panied by a copy of a valid, full-time student ID.


_______________________________________________________________________________


ISCA'97 Registration Form


First Name: ____________________________ Last Name: __________________________


Organization:__________________________________________________________________


Address: ______________________________________________________________________


                  ______________________________________________________________________


City: _______________________ State: ________________ Postal Code: _________


Country: ______________________________________________________________________


Phone: _______________________


E-mail Address: _______________________________________________________________


IEEE/ACM Membership Number: ___________________________________________________


Information on Name Badge: ___________________________________________________


                                                        ___________________________________________________


Do you have any special requirements? _________________________________________


===============================================================================


Registration Fees - Please circle the appropriate fee(s):


                                        Advance (by May 1) Late/On-Site
                            Student Member Non-Member Student Member Non-Member


Conference $125 $350 $440 $150 $425 $515


Tutorials/
Workshops
        T1 $45 $185 $230 $70 $215 $265


        T2 $45 $185 $230 $70 $215 $265


        T3 $45 $185 $230 $70 $215 $265


        T4 $45 $185 $230 $70 $215 $265


        W1 $100 $260 $320 $125 $315 $390


        W2 $100 $260 $320 $125 $315 $390


Number of additional banquet tickets (at $50 each): __________


Total Fees: ____________


IEEE-CS or ACM membership numbers must be included to qualify for member regis-
tration rate. For students, a copy of a valid full-time student ID must be
included. No refunds unless a written cancellation request is received before
May 14, 1997. All refunds are subject to a $35 fee. All registrations after
May 14, 1997 will be processed on site only, fee must be enclosed.


===============================================================================


Payment Method (please circle one):


    Check enclosed (make check payable to ISCA'97)


    Visa MasterCard American Express


    Card Number:__________________________________________ Exp. Date:_________


    Cardholder Name:__________________________________________________________


    Signature:________________________________________________________________




===============================================================================


Please mail or FAX the completed form to:


ISCA '97 Registration
Dept. of Computer Science
Campus Box 430
Boulder, CO 80309-0430
Fax:(303) 492-2844
Email: isca97@boulder.colorado.edu


*******************************************************************************


Hotel Information


All technical sessions, tutorials, registration and banquet luncheon will be
held at the Westin Hotel, Tabor Center in downtown Denver. The Westin is cen-
trally located in downtown Denver and is within walking distance of many res-
taurants and shops. (It is also about a mile away form Coors Field, home of
the Colorado Rockies.) Reservations must be made directly with the Westin.


Please send your reservation form directly to:


        The Westin Hotel, Tabor Center Denver
        Attention: Reservations
        1672 Lawrence Street
        Denver, CO 80202
        or FAX it to: (303) 572-7288


Reservations may also be made by phone by calling:


        1-800-228-3000 for world-wide reservations
        (303) 572-9100 for the hotel directly


When calling use the keyword ISCA97.


Rates are $135 for single or double occupancy rooms. There are a limited
number of double occupancy rooms, so if you think you will be sharing a room,
make sure you call early.
_______________________________________________________________________________


ISCA'97 Hotel Registration Form


First Name: ____________________________ Last Name: __________________________


Sharing with:
    First Name:____________________________ Last Name: __________________________


Organization:__________________________________________________________________


Address: ______________________________________________________________________


                  ______________________________________________________________________


City: _______________________ State: ________________ Postal Code: _________


Country: ______________________________________________________________________


Phone: ________________________


Arrival Date/Time: ____________________ Departure Date/Time: __________________


===============================================================================


Room Preference (please circle one):


            Single at $135 per night or Double at $135 per night


===============================================================================


Payment Method (please circle one):


    Check enclosed (make check payable to ISCA'97)


    Visa MasterCard Carte Blance Diner's Club American Express


    Card Number: ______________________________________ Exp. Date:___________


    Cardholder Name:____________________________________________________________


    Signature: ____________________________________________________________


===============================================================================


Please mail the completed form to:


The Westin Hotel, Tabor Center Denver
Attention: Reservations
1672 Lawrence Street
Denver, CO 80202


or FAX it to: (303) 572-7288


*******************************************************************************


Conference World-Wide Web Site: http://arch.cs.ucdavis.edu/ISCA97
_______________________________________________________________________________


Weather


The weather in Denver at the beginning of June is typically warm and sunny,
with daytime temperatures between 70F and 80F, and nighttime lows of between
45F and 55F. Although Denver is dry in the summer, there is very good chance
of late afternoon thunderstorms. On our excursion, we will be going up into
the mountains where the weather can be very unpredictable.
_______________________________________________________________________________


Transportation


Regularly scheduled buses run from Denver International Airport (DIA) to the
downtown Denver area. The main regional bus station is within a two block walk
of the hotel (the local bus service is known as the RTD). Taxis are also
available as well as shuttle buses for the major downtown hotels. Renting a
car should not be necessary, unless you are planning to do some traveling in
the are before or after the conference.


*******************************************************************************


Conference Officials
---------------


General Chair: Andrew R. Pleszkun, University of Colorado
Program Chair: Trevor N. Mudge, University of Michigan
Tutorials Chair: Michael D. Smith, Harvard University
Publicity Chair: Matthew K. Farrens, University of California, Davis
Local Arrangements: Dirk Grunwald, University of Colorado


Steering Committee
---------------


Joel Emer, DEC Allan Gottlieb, NYU Guri Sohi, UW-Madison
Mike Flynn, Stanford Yale Patt, Univ. of Michigan


Program Committee
---------------


Anant Agarwal Gul Agha Forrest Baskett
MIT Illinois SGI


Brian Bershad Laxmi Bhuyan Peter Chen
Washington Texas A&M Michigan


Paul Chow Tom Conte Joel Emer
Toronto North Carolina State DEC


Matt Farrens Dirk Grunwald John Gurd
UC Davis Colorado Manchester


Mark Hill Wen-mei Hwu Monica Lam
Wisconsin Illinois Stanford


Steve Melvin David Nagle Lionel Ni
Zytek CMU Michigan State


Kunle Olukotun David Patterson Stuart Sechrest
Stanford UC Berkeley Michigan


Mike Smith Per Stenstrom Nigel Topham
Harvard Chalmers Edinburgh


Mateo Valero David Wood Robert Yung
Politecnica de Catalunya Wisconsin Sun Microsystems


Willy Zwaenepoel
Rice


Conference World-Wide Web Site: http://arch.cs.ucdavis.edu/ISCA97


*******************************************************************************


There are two workshops that may be of interest to conference attendees. They
are being held at the Oxford Hotel, 2 blocks away from the conference hotel.


---------------
Wednesday, June 4th, 1997


2:00 Academic Careers Workshop


The Computing Research Association's Academic Careers Workshop covers the
tenure process, networking with other researchers, selecting and managing a
research program, getting funding, and time management/family issues. Its tar-
get audience is faculty in the beginning years of their careers and senior gra-
duate students contemplating an academic career. This workshop ends at noon
Thursday. See the workshop page for more details, including how to register.
(http://www.cra.org/Activities/conferences/workshops.htm) (Organized by David
A. Patterson.)


---------------
Thursday, June 5th 1997


2:00 Teaching in Computer Science and Engineering Workshop


The purpose of the Computing Research Association's Effective Teaching in Com-
puter Science and Engineering Workshop is to help new faculty members teach
more effectively. This highly interactive workshop includes theoretical
material on learning styles and instructional objectives, and practical tips on
effective lecturing, creative problem-solving and collaborative learning. This
workshop ends at noon Friday. See the workshop page
(http://www.cra.org/Activities/conferences/effectiv.htm) for more details,
including how to register. (Organized by Michael R. Williams.)
--

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