compiler optimization for power reduction

Vijay Ganesh <vgee@india.ti.com>
7 Feb 1997 23:40:24 -0500

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compiler optimization for power reduction vgee@india.ti.com (Vijay Ganesh) (1997-02-07)
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From: Vijay Ganesh <vgee@india.ti.com>
Newsgroups: comp.compilers
Date: 7 Feb 1997 23:40:24 -0500
Organization: texas instruments india limited
Keywords: architecture, question

Hi,


As System On Chip Is Becoming A Reality Power Consumption Is Becoming
A Major Concern. I Know Of Some Work In The Area Of Compiler
Optimizations For Reduction In Power Consumptions. Can Anybody Point
Me To More Such Sources. I Have Read That In The Apple'S Newton
Product, They Reduced Power Consumption By 20% By Optimizing The
Code. (Essentially Increasing Cache Hits). Please Send In Any Source
You Know Of.


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Vijay Ganesh Software Development Systems (SDS)
vgee@india.ti.com Texas Instruments (india) ltd.
Golf View Homes,
Murgeshpalaya,
Bangalore-17.
Phone :- 5269451 extn 809
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