Related articles |
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made up byte code: registers vs. literals jklein@freon.artificial.com (1996-11-24) |
Re: made up byte code: registers vs. literals bear@sonic.net (Ray S. Dillinger) (1996-12-01) |
Re: made up byte code: registers vs. literals cliffc@risc.sps.mot.com (1996-12-03) |
Re: made up byte code: registers vs. literals kaleja@rahul.net (Russell Bornsch++) (1996-12-03) |
From: | cliffc@risc.sps.mot.com (Cliff Click) |
Newsgroups: | comp.compilers |
Date: | 3 Dec 1996 20:46:28 -0500 |
Organization: | none |
References: | 96-11-149 96-12-020 |
Keywords: | architecture, optimize |
"Ray S. Dillinger" <bear@sonic.net> writes:
> In a RISC architecture there *are no* instructions that deal with literals,
> except one: it loads a literal value into a register. Also, there are
> exactly two instructions that deal with main memory; load and store.
Actually, most RISC ISAs fold 1 add in with the load and store;
either add 2 registers or add a register and literal. This follows
from having 2 addressing modes available on most instructions:
reg+reg and reg+literal.
Cliff
--
Cliff Click, Ph.D. Compiler Researcher & Designer
RISC Software, Motorola PowerPC Compilers
cliffc@risc.sps.mot.com (512) 891-7240
http://members.aol.com/mjclick1
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