Re: Transport Triggered Architectures

tm2@nntp1.best.com (Toshi Morita)
1 Nov 1996 17:47:01 -0500

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Transport Triggered Architectures RDREILIN@mailgw.sanders.lockheed.com (RDREILIN) (1996-10-30)
Re: Transport Triggered Architectures tm2@nntp1.best.com (1996-11-01)
Re: Transport Triggered Architectures anton@a0.complang.tuwien.ac.at (1996-11-01)
Re: Transport Triggered Architectures tm2@nntp1.best.com (1996-11-05)
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From: tm2@nntp1.best.com (Toshi Morita)
Newsgroups: comp.compilers
Date: 1 Nov 1996 17:47:01 -0500
Organization: Best Internet Communications
References: 96-10-159
Keywords: architecture

RDREILIN (RDREILIN@mailgw.sanders.lockheed.com) wrote:
: Looking for references and info to this special architecture especially
: software development tools and compilers.


I think there were two articles on it, one in Compiler Construction
'92 and one in '94. There's some guys working on it at the University
of Delft, I think.


In a nutshell, I would describe it as a post-VLIW architecture with
the paradigm shift where your opcode bits are controlling the data bus
routing inside the processor instead of the functional units
themselves.


Since I don't know of any actual commercial processors which are TTA,
I think you're a little premature in your inquiry about software
development tools and compilers. :) If I remember correctly, most of
the work so far had been done on an simulation of an i860 with a
TTA-style architecture.


Toshi
--

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