Micro-29 advance program

beaty@hpfcla.fc.hp.com (Steve Beaty)
5 Sep 1996 23:57:20 -0400

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Micro-29 advance program beaty@hpfcla.fc.hp.com (1996-09-05)
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From: beaty@hpfcla.fc.hp.com (Steve Beaty)
Newsgroups: comp.compilers,comp.arch,comp.parallel
Date: 5 Sep 1996 23:57:20 -0400
Organization: Hewlett-Packard Fort Collins Site
Keywords: conference, parallel, architecture

                                                                Advance Program
            29th Annual International Symposium on Microarchitecture (Micro-29)

                                              Paris, France, December 2-4, 1996
                              Ecole Nationale Superieure des Telecommunications

Monday, 2 December 1996

Session 1
A Persistent Rescheduled-Page Cache for Low Overhead Object Code
Compatibility in VLIW Architectures
Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia, North
Carolina State University

Integrating a Misprediction Recovery Cache (MRC) Into a Superscalar Pipeline
James O. Bondi, Texas Instruments and Ashwini K. Nanda, IBM and
Simonjit Dutta, Texas Instruments

Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching
Eric Rotenberg, University of Wisconsin and Steve Bennett,
Intel and Jim Smith, University of Wisconsin

Session 2
Accurate and Practical Profile-Driven Compilation using the Profile Buffer
Thomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch, North
Carolina State University

Efficient Path Profiling
Thomas Ball, Bell Laboratories and James R. Larus, University
of Wisconsin

Profile-Driven Instruction Level Parallel Scheduling with Application to
Super Blocks
C. Chekuri, R. Motwani, Stanford University and R. Johnson, B.
Natarajan, B. R. Rau, M. Schlansker, Hewlett-Packard Laboratories

Session 3
Speculative Hedge: Regulating Compile-Time Speculation Against Profile
Brian L. Deitrich, Wen-mei W. Hwu, University of Illinois

Hot Cold Optimization of Large Windows/NT Applications
Robert Cohn, P. Geoffrey Lowney, Digital Equipment Corporation

Java Bytecode to Native Code Translation: the Caffeine Prototype and
Preliminary Results
Cheng-Hsueh A. Hsieh, John C. Gyllenhaal, Wen-mei W. Hwu,
University of Illinois

Session 4
Analysis Techniques for Predicated Code
Richard Johnson, Michael Schlansker, Hewlett-Packard Laboratories

Global Predicate Analysis and its Application to Register Allocation
David M. Gillies, Dz-ching Roy Ju, Richard Johnson, Michael
Schlansker, Hewlett-Packard

Modulo Scheduling of Loops in Control-Intensive Non-Numerical Programs
Daniel M. Lavery, Wen-mei W. Hwu, University of Illinois

18h00 - 20h00 Wine/Cheese Buffet - ENST
20h00 - 22h00 Business Meeting, Shoot Out - ENST

Tuesday, 3 December 1996

Session 5
Assigning Confidence to Conditional Branch Predictions
Erik Jacobsen, Eric Rotenberg, Jim Smith, University of Wisconsin

Compiler Synthesized Dynamic Branch Prediction
Scott Mahlke and Balas Natarajan, Hewlett-Packard Laboratories

Wrong-Path Instruction Prefetching
Jim Pierce, Intel and Trevor Mudge, University of Michigan

Session 6
Design Decisions Influencing the UltraSPARC's Instruction Fetch Architecture
Robert Yung, Sun Microsystems Inc.

Increasing the Instruction Fetch Rate via Block-Structured Instruction Set
Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt, University
of Michigan

Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings
Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N.
Menezes, Sumedh W. Sathaye, North Carolina State University

Session 7
Tango: a Hardware-based Data Prefetching Technique for Superscalar Processors
Shlomit S. Pinter, IBM Haifa, and Adi Yoaz, Intel Israel

Exceeding the Dataflow Limit Via Value Prediction
Mikko H. Lipasti, John Paul Shen, Carnegie Mellon University

The Performance Potential of Data Dependence Speculation & Collapsing
Yiannakis Sazeides, University of Wisconsin, and Stamatis
Vassiliadis, Delft University of Technology, and James E. Smith,
University of Wisconsin

Session 8
Heuristics for Register-constrained Software Pipelining
Josep Llosa, Mateo Valero, Eduard Ayguade, Universitat Politecnica
de Catalunya

Software Pipelining Loops with Conditional Branches
Mark G. Stoodley, Corinna G. Lee, University of Toronto

Combining Loop Transformations Considering Caches and Scheduling
Michael E. Wolf, Dror E. Maydan, Ding-Kai Chen, Silicon Graphics

20h00 - 23h00 Banquet

Wednesday, 4 December 1996

Session 9
Instruction Scheduling and Executable Editing
Eric Schnarr, James R. Larus, University of Wisconsin

Instruction Scheduling for the HP PA-8000
David A Dunn, Wei-Chung Hsu, Hewlett-Packard

Meld Scheduling: Relaxing Scheduling Constraints Across Region Boundaries
Santosh Abraham, Vinod Kathail, Hewlett-Packard Laboratories and
Brian Deitrich, University of Illinois

Session 10
Custom-Fit Processors: Letting Applications Define Architectures
Joseph A. Fisher, Paolo Faraboschi, Giuseppe Desoli,
Hewlett-Packards Laboratories

Optimization for a Superscalar Out-of-Order Machine
Anne M. Holler, Hewlett-Packard

Optimization of Machine Descriptions for Efficient Us
John C. Gyllenhaal, Wen-mei W. Hwu, University of Illinois and
B. Ramakrishna Rau, Hewlett Packard Laboratories

12h15 - 13h15 Concluding Remarks, Awards, Etc.

Steve Beaty beaty@fc.hp.com
Hewlett-Packard beaty@lance.colostate.edu
Fort Collins, Colorado, USA http://www.lance.colostate.edu/~beaty/

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