Re: Using memory above TOS

markt@harlequin.co.uk (Mark Tillotson)
29 May 1996 21:05:19 -0400

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Re: Using memory above TOS bart@time.cirl.uoregon.edu (1996-05-19)
Using memory above TOS fjh@cs.mu.OZ.AU (Fergus Henderson) (1996-05-21)
Re: Using memory above TOS jeremy@floyd.sw.oz.au (1996-05-21)
Re: Using memory above TOS markt@harlequin.co.uk (1996-05-29)
Re: Using memory above TOS markt@harlequin.co.uk (1996-05-29)
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From: markt@harlequin.co.uk (Mark Tillotson)
Newsgroups: comp.compilers
Date: 29 May 1996 21:05:19 -0400
Organization: Harlequin Limited, Cambridge, England
References: 96-05-132 96-05-142
Keywords: architecture

jeremy@floyd.sw.oz.au (Jeremy Fitzhardinge) claimed:


> Trying to use memory below the stack on a SPARC completely
> fails, because the stack is generally not used directly, but
> kept cached in register windows. The kernel takes the liberty
> of not saving register windows "below" the SP on context
> switches. In other words, you can't really defer the
> use of a "save" instruction if you need to store things on the stack.


Oh yes you can. You just have to avoid storing stuff where the windows
will be dumped (if you want it back again!), and use a separate signal
stack. The kernel's only checks on flushing the windows are that each
register window is saved at a double-word aligned address in valid
writeable address space.


Having implemented portions of a compiler back-end and light-weight
process switching on the Sparc, I do know what I'm talking about!


__Mark
[ markt@harlequin.co.uk | http://www.harlequin.co.uk/ | +44 1223 873829 ]
[ homepage http://www.hal.com/services/juggle/home/markt@harlequin.co.uk/ ]


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