Related articles |
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Re: Q: P6 branch prediction conway@rimmer.cs.mu.OZ.AU (1996-05-01) |
Re: Q: P6 branch prediction khays@sequent.com (1996-05-14) |
Re: Using memory below the SP (Was: Q: P6 branch prediction) zalman@macromedia.com (1996-05-18) |
Re: Using memory above TOS bart@time.cirl.uoregon.edu (1996-05-19) |
Using memory above TOS fjh@cs.mu.OZ.AU (Fergus Henderson) (1996-05-21) |
Re: Using memory above TOS jeremy@floyd.sw.oz.au (1996-05-21) |
Re: Using memory above TOS markt@harlequin.co.uk (1996-05-29) |
Re: Using memory above TOS markt@harlequin.co.uk (1996-05-29) |
From: | markt@harlequin.co.uk (Mark Tillotson) |
Newsgroups: | comp.arch,comp.compilers |
Date: | 29 May 1996 21:04:05 -0400 |
Organization: | Harlequin Limited, Cambridge, England |
References: | <3179B05D.2781@cs.princeton.edu> 96-05-012 96-05-100 96-05-105 96-05-132 |
Keywords: | architecture |
> P.S. -- Actually, now that I think about it, the main reason I
> avoided memory above TOS is that I wasn't sure that UNIX
> promised to keep pages above TOS backed up in VM; i.e., if TOS
> was sitting at a page boundary, the page above might be paged
> out at an arbitrary time, and then be reallocated zero-filled
> when next referenced, losing the contents of words above TOS.
I've never heard of that - the pager isn't going to check which
user-mode register was responsible for generating a virtual address,
it will just deal with the fault and restart the instruction. You
certainly wouldn't be able to implement thread-libraries if the kernel
looked at the stack pointer!!
__Mark
[ markt@harlequin.co.uk | http://www.harlequin.co.uk/ | +44 1223 873829 ]
[ homepage http://www.hal.com/services/juggle/home/markt@harlequin.co.uk/ ]
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