Re: Compile HLL to microcode on VLIW - possible?

Preston Briggs <preston@tera.com> wrote:
>And that's the whole deal. With instruction caches, you can make the
>hardwired instruction cycle as fast as microcode. There's no reason
>to have a separate level of instruction interpretation.


andy@Xenon.Stanford.EDU (Andy Freeman) writes:
] That assumes that the only purpose of microcode is sequencing and
] composition. While sequencing is the mechanism, is it really the only
] worthwhile purpose? (Given the PALcode example, protected sequencing
] isn't a microcode exclusive.) I can't think of others, but ....


Imagine an era where logic/processor speeds are outstripping memory
speed. A compactly coded instruction set will lead to a lower I-cache
miss rate from a fixed size cache or the same per-instruction miss
rate from a smaller cache. The gain from either of these may easily
justify the cost of complex decoding and/or microcoded execution.


Or, in buzzword, CISC may help when we hit the memory wall.


This is an example of why many believe there is no "best architecture"
: the underlying implementation technology keeps changing, and this
changes which architectures can be efficiently executed at high speed.
--
Dennis O'Connor doconnor@sedona.intel.com
[Are we swinging back to a slow memory era again? Considering how hard
people are working on cache designs, I guess so. -John]
--

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