Related articles |
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Re: Compile HLL to microcode on VLIW - possible? narad@nudibranch.asd.sgi.com (1996-04-10) |
The shortest way with programs (was Compile HLL to microcode) dlmoore@ix.netcom.com (1996-04-18) |
Re: The shortest way with programs (was Compile HLL to microcode) krste@ICSI.Berkeley.EDU (1996-04-19) |
From: | krste@ICSI.Berkeley.EDU (Krste Asanovic) |
Newsgroups: | comp.arch,comp.compilers |
Date: | 19 Apr 1996 12:11:59 -0400 |
Organization: | International Computer Science Institute, Berkeley, CA, U.S.A. |
References: | 96-04-059 96-04-111 |
Keywords: | architecture, performance |
dlmoore@ix.netcom.com (David L Moore) writes:
|> One of the other features of RISC was, of course, that the silicon
|> freed up by simplifying the instruction set could be used for more
|> registers. Modern CISC chips use REGISTER RENAMING to achieve the same
|> thing. That is, even though you think you only have 6 useful
|> registers, you really have more because when you assign to a register,
|> it is given a new name in the register file.
One more time: Adding rename registers is not equivalent to adding
more logical registers, or vice versa. They have different effects.
Consider:
If there are not enough logical registers available to perfectly
allocate a routine, the compiler must generate spill code.
Regardless of the number of rename registers the machine must
execute the extra loads and stores.
Even if there are a surplus of logical registers, a poorly
scheduled routine may contain WAR or WAW dependencies that
register renaming could remove.
--
Krste Asanovic phone: +1 (510) 642-4274 x143
International Computer Science Institute fax: +1 (510) 643-7684
Suite 600, 1947 Center Street email: krste@icsi.berkeley.edu
Berkeley, CA 94704-1198, USA http://www.icsi.berkeley.edu/~krste
--
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