Re: performance measurement and caches

Terje Mathisen <Terje.Mathisen@hda.hydro.com> writes:
>I believe this is mostly due to the way 486, Pentium and PPro handles
>code prefetching, both 486 and PPro really likes to have the top of
>busy loops aligned near the beginning of a cache line, i.e. you can
>get this effect in single-tasking mode, with no system traffic at all.
>
>The Pentium relaxed the branch target requirement to 32-bit boundaries.


Actually, this is not true. Even though I think that I said this in my
book and I think Intel has said this too. If an instruction straddles
a cache line boundary and it is, for example, the top instruction in a
loop you will loose performance. Usually, a 4-byte boundary will work
OK. But if the instruction is 5 bytes in length, then 1 out of 8
times their will be a delay.


Mike Schmit
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mschmit@ix.netcom.com author:
408-244-6826 Pentium Processor Programming Tools
800-765-8086 ISBN: 0-12-627230-1
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