Related articles |
---|
Compiler back-ends [Q] Ben.Sloman@reading.ac.uk (1995-10-21) |
Re: Compiler back-ends [Q] cliffc@ami.sps.mot.com (1995-10-23) |
Re: Compiler back-ends [Q] pardo@cs.washington.edu (1995-10-25) |
Re: Compiler back-ends [Q] jgj@ssd.hcsc.com (1995-10-27) |
Re: Compiler back-ends [Q] collberg@cs.aukuni.ac.nz (1995-10-29) |
Re: Compiler back-ends [Q] Martin.Jourdan@inria.fr (1995-11-03) |
Re: Compiler back-ends [Q] sc@iaxp01.inf.uni-jena.de (Sebastian Schmidt) (1995-11-03) |
Re: Compiler back-ends [Q] cliffc@ami.sps.mot.com (1995-11-03) |
Newsgroups: | comp.compilers |
From: | Sebastian Schmidt <sc@iaxp01.inf.uni-jena.de> |
Keywords: | code |
Organization: | Compilers Central |
References: | 95-11-017 95-10-114 |
Date: | Fri, 3 Nov 1995 09:44:34 GMT |
cliffc@ami.sps.mot.com (Cliff Click) writes:
>Note that this is a _far_ cry from having the entire backend generated
>automatically. It's just instruction selection and some peephole
>opts. Register allocation is an amazing can of worms, and I don't know
>of any machine-generated code techniques being used there.
collberg@cs.aukuni.ac.nz (Christian Collberg) writes:
>The BEG back-end generator automatically generates a register
>allocator based on a description of the register set (register
>names, register classes, double registers, etc). You also get
>a choice between a fast/dumb and a slow/smart allocator.
There is also the Marion system. It generates a backend doing
instruction selection, instruction scheduling and register allocation
from a machine description.
@Article{ bradlee:91a,
author = "David G.~Bradlee and Susan J.~Eggers and Robert
R.~Henry",
title = "The marion system for retargetable instruction
scheduling",
volume = 26,
number = "6",
pages = "229--240",
note = pldi91,
journal = sigplan,
year = 1991,
month = jun,
organization = acm,
address = "Toronto, Ontario, Canada"
}
--
e-mail: sc@iaxp01.inf.uni-jena.de
phone: (+49) 3641 631398
fax: (+49) 3641 631400
May your disk buffers flush before powerdown!
--
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