Invitation to Workshop on Interaction of Compilers and Computer Architectures

Here I forward a mail, an invitation to the workshop on interaction of
compilers and computer architectures. It will be held in conjuction of HPCA-2.
Refer to the attachment.


SC
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Sangyeun Cho
Dept. of Computer Science
Univ. of Minnesota
mailto:sycho@cs.umn.edu
http://www.cs.umn.edu/~sycho
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You are cordially invited to participate in the Workshop on
Interaction between Compilers and Computer Architectures.
As described in the call-for-papers below, the
workshop will be held in conjunction with the Second International
Symposium on High-Performance Computer Architectures (HPCA-2 - San Jose,
CA. Feb. 4-7, 1996).
We believe that the workshop will be an exciting forum to exchange
new ideas and recent developments in compiler techniques and
computer architectures that enhance each other's capabilities and
performance. We urge you to participate in this exciting workshop.


Regards,
Gyungho Lee and Pen -C. Yew


********************* (CALL FOR PAPERS) ****************


        "Workshop on Interaction between Compilers and Computer Architectures"


Organizers: G. Lee and P.-C. Yew, University of Minnesota


in conjunction with the


Second International Symposium on
High-Performance Computer Architecture
San Jose, California - February 4 - 7, 1996


Sponsored by the IEEE Computer Society


THEME:
Effective compilers will allow more efficient execution of
application programs on a given computer architecture.
On the other hand, well conceived architectural features
can support more effective compiler optimization techniques.
   Good interaction between compilers and computer architectures
is key to the success of designing highly efficient
and effective computer systems. This workshop is to promote
new ideas and to present recent developments in compiler
techniques and computer architectures that enhance each other's
capabilities and performance.
Papers are solicited on any aspect of interaction between
compilers and architectures in the design of microprocessors,
multiprocessors, and other parallel computer systems.


A partial list of the potential topics,
as broadly categorized, includes:


> Code Generation and Scheduling
> Memory, Cache, and Register Management
> Speculative and Predicated Execution
> Parallelism Enhancement and Exploitation
> Efficient I/O Operations
> Experiences in Optimizing Compilers
> Runtime Support
> Task Synchronization and Scheduling


Contribution Submissions:


Submit a copy of the abstract of your contribution including
e-mail address, and fax number, to either of the organizers:
Electronic submission (ASCII or Postscript) is preferred.


Prof. Gyungho Lee Prof. Pen.-C. Yew
Dept. of Electrical Engineering Dept. of Computer Science
University of Minnesota University of Minnesota
200 Union St. S.E. 200 Union St. S.E.
Minneapolis, MN 55455 Minneapolis, MN 55455
e-mail: ghlee@ee.umn.edu e-mail: yew@cs.umn.edu


Important Dates:
Submission due by December 4, 1995
Author Notification due by January 5, 1995
Final Presentation Material due by January 26, 1996


NOTE:
(1). Although there will be no proceedings for the workshop,
the collection of the final presentation materials will be
copied and distributed to the participants.
(2). For more information regarding the HPCA-2 and the workshop,
see WWW home page: //www-mount.ee.umn.edu/~dice/workshop.html
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