Re: Compiler support for a faster interrupt response

David Whalley <whalley@sed.cs.fsu.edu>
Fri, 29 Sep 1995 11:16:35 GMT

          From comp.compilers

Related articles
Re: Compiler support for a faster interrupt response ah739@cleveland.Freenet.Edu (1995-09-29)
Re: Compiler support for a faster interrupt response whalley@sed.cs.fsu.edu (David Whalley) (1995-09-29)
Re: Compiler support for a faster interrupt response mav@sleepy.local.org (1995-09-29)
Re: Compiler support for a faster interrupt response sethml@sloth.ugcs.caltech.edu (1995-10-03)
Re: Compiler support for a faster interrupt response gary@Intrepid.COM (1995-10-06)
Re: Compiler support for a faster interrupt response hdlambri@cs.arizona.edu (Henry Dan Lambright) (1995-10-26)
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Newsgroups: comp.compilers
From: David Whalley <whalley@sed.cs.fsu.edu>
Keywords: optimize, architecture
Organization: Compilers Central
References: 95-09-154
Date: Fri, 29 Sep 1995 11:16:35 GMT

Ji Hoon Yoon stated:


      Whenever interrupt occurs, it is basically true that
      all global registers should be saved in the interrupt
      prolog and restored in the epilog.


      But in the case of 29K processor, nearly 40 ~ 50 registers
      should be saved and restored at each interrupt, which, of course,
      increses the interrupt response time.


      Thus I want to survey various existing techniques for conquering this
      heavy register saving/restoring problem.
      Would you help me?


I suggest you look at the article:


%A J. Snyder
%A D. B. Whalley
%A T. P. Baker
%T Fast Context Switches: Compiler and Architectural Support for Preemptive Scheduling
%J Microprocessors and Microsystems
%V 19
%N 1
%D February 1995
%P 35-42


We reduced the number of registers that would require saving and restoring
at context switch points. You can access the postscript for this paper
at either ftp.cs.fsu.edu:/pub/whalley/papers/mnm95.ps.Z or in
http://www.cs.fsu.edu/~whalley.


Dave
--


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