Re: Supporting byte-addressability on word-addressed hardware

lehotsky@tiac.net (Alan Lehotsky) wrote:
> I'm beginning a project to modify a gcc port to a machine that only
> support 32-bit word addressed memory. At present, the port treats
> ints, shorts and chars as the same size objects.


Is this current scheme actually a problem??? How much space really is
wasted? Is it significant? Is speed or size more important anyhow?


> The "modification" is to add support for byte and short addresses.
> Because of the memory layout, we can effectively address all memory
> with a 30-bit word address.


The best way to add support is to use byte addresses uniformly, and
shift them right to get the word address on every dereference. Thus
each pointer is 30 msbs of word pointer and 2 lsbs of byte indicator.


(You do realize how expensive stores of char and short will be?!?---it
  is almost certainly worth making spills of these values aligned as
  whole words so spill code doesn't have to fiddle around extracting
  bytes!)


This avoids all of your problems, at the expense of a shift before
every deference (ie a few modications of the RTL generator??).
Perhaps some of these shifts can be CSE-optimized out (I don't know
enough about gcc to comment on the feasibility of this)


The only gotcha with my scheme is its incompatibility with native
word pointers (this might hit you in the OS interface/library?)


Mark




| Mark Tillotson | Harlequin Ltd. | markt@harlequin.co.uk |
| http://www.harlequin.co.uk/ | +44 1223 873829 |
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