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| EURO-PAR'95: Call for participation and advance programme (long) psm@sics.se (1995-06-14) |
| Newsgroups: | comp.parallel,comp.compilers,comp.arch |
| From: | psm@sics.se (Peter Magnusson) |
| Followup-To: | europar95registration@sics.se |
| Keywords: | conference, parallel |
| Organization: | Swedish Institute of Computer Science, Kista |
| Date: | Wed, 14 Jun 1995 10:45:44 GMT |
| Status: | RO |
+------------------------------+
| CALL FOR PARTICIPATION |
| and |
| ADVANCE PROGRAMME |
| |
| EURO-PAR'95 |
+------------------------------+
Stockholm, Sweden
August 29-31, 1995
International Conference on Parallel Processing
Merging PARLE and CONPAR-VAPP
Swedish Institute of Computer Science (SICS) and
Department of Teleinformatics, KTH
in cooperation with:
ERCIM
IEEE CA & PP
European Commission
Gesellschaft fuer Informatik/PARS
Parallel processing is a discipline of strategic significance within the
Information Technology sector. EURO-PAR'95 is the first conference that merges
the two international conferences on parallel processing: PARLE and CONPAR-
VAPP. EURO-PAR annual conferences will cover the full spectrum of parallel
processing, ranging from theory to design and applications. The objective is
to provide a forum within which to promote the development of parallel
computing, both as an industrial technique and an academic discipline,
extending the frontier of both the state of the art and the state of the
practice. EURO-PAR'95 will include a vendor exhibition and workshops.
EXECUTIVE SUMMARY
=================
* early registration deadline: July 31st
* conference fee: 3400 SEK for non-student, 1700 SEK for student
(after July 31st the fee is 3800 SEK and 1900 SEK, respectively)
* conference web site: "http://www.sics.se/europar95"
* send e-mail to "europar95info@sics.se" to join (low-bandwidth) mailing list
* keynote speakers: Greg Papadopoulos, Gert Smolka, and Bjorn Engquist
* 50 papers and 11 posters
* 5 tutorials
* workshop on shared-memory multiprocessors
* proceedings will be available on the WWW for participants
* hardcopy of proceedings will be published by Springer-Verlag
TABLE OF CONTENTS
=================
1 - Preliminary Program (Overview)
2 - Keynote Speakers
3 - Preliminary Program - Paper Sessions
4 - Poster Session
5 - Vendor Session
6 - Proceedings on the WWW
7 - Tutorials
8 - Steering Committee
9 - Programme Committee
10 - Organizing Committee
11 - Workshop Shared-Memory Multiprocessors
12 - Registration Fees and Payment
13 - Hotel Information
14 - Tourist Information
15 - EURO-PAR'96
16 - Contact Information
1 PRELIMINARY PROGRAM - OVERVIEW
=================================
August 27 (Sunday)
==================
------------------------------------------------------------
| |
| Workshop: "Shared-Memory Multiprocessors" |
| |
------------------------------------------------------------
August 28 (Monday)
==================
8:00 - 10.00 Registration
------------------------------------------------------------
9:00 - 10:30 | Tutorial 1 | Tutorial 2 | Tutorial 4 |
------------------------------------------------------------
10:30 - 11:00 Coffee Break
------------------------------------------------------------
11:00 - 12:30 | Tutorial 1 | Tutorial 2 | Tutorial 4 |
------------------------------------------------------------
12:30 - 14:00 Lunch
------------------------------------------------------------
14:00 - 15:30 | Tutorial 1 | Tutorial 3 | Tutorial 5 |
------------------------------------------------------------
15:30 - 16:00 Coffee Break
------------------------------------------------------------
16:00 - 17:30 | Tutorial 1 | Tutorial 3 | Tutorial 5 |
------------------------------------------------------------
17:00 - 19:30 Registration
August 29 (Tuesday)
===================
8:00 - Registration
------------------------------------------------------------
8:45 - 9:00 | Opening |
------------------------------------------------------------
9:00 - 10:00 | Keynote: Greg Papadopoulos, Sun Microsystems |
------------------------------------------------------------
10:00 - 10:30 Coffee Break
------------------------------------------------------------
10:30 - 12:30 | Language Implementation I | Architecture Design |
------------------------------------------------------------
12:30 - 14:00 Lunch
------------------------------------------------------------
14:00 - 16:00 | Semantics and tools | Interconnection Networks I |
------------------------------------------------------------
16:00 - 16:30 Coffee Break
------------------------------------------------------------
16:30 - 18:00 | Parallel Algorithms I | Cache Systems |
------------------------------------------------------------
18:30 Departure for Reception
19:00 - 21:30 Welcome Reception
August 30 (Wednesday)
=====================
------------------------------------------------------------
9:00 - 10:00 | Keynote: Gert Smolka, DFKI |
------------------------------------------------------------
10:00 - 10:30 Coffee Break
------------------------------------------------------------
10:30 - 12:30 | Loop Parallelization | Load Bal. & Par. Alg. II | V. S. |
------------------------------------------------------------
12:30 - 14:00 Lunch
------------------------------------------------------------
14:00 - 16:00 | Compiling Techniques | Applications | P. S. |
------------------------------------------------------------
------------------------------------------------------------
16:00 - 17:00 | Best Paper |
------------------------------------------------------------
17:30 Departure for Banquet
18:00 - 22:00 Banquet
August 31 (Thursday)
====================
------------------------------------------------------------
9:00 - 10:00 | Keynote: Bjorn Engquist, KTH and UCLA |
------------------------------------------------------------
10:00 - 10:30 Coffee Break
------------------------------------------------------------
10:30 - 12:00 | Language Implementation II | Interconnection Networks II |
------------------------------------------------------------
12:00 - 13:30 Lunch
------------------------------------------------------------
13:30 - 15:00 | Scheduling | Fault Tolerance and SIMD Array|
------------------------------------------------------------
------------------------------------------------------------
15:15 - 16:15 | Panel Discussion: Future of Parallel Processing |
------------------------------------------------------------
"P.S." = Poster Session (see section 4)
"V.S." = Vendor Session (see section 5)
2 KEYNOTE SPEAKERS
===================
Tuesday: Greg Papadopoulos, "Mainstream Parallelism: Taking Sides
++++++++++++++++++++++++++ on the SMP/MPP/Cluster Debate"
Greg Papadopoulos (Ph.D., MIT EECS) is the Chief Technology Officer for Sun
Microsystems' Server Group. He has spent the last fifteen years developing
scalable general and special purpose systems. Prior to joining Sun in the Fall
1994, he was Senior Architect at Thinking Machines Corporation and an
Associate Professor at MIT. In addition, Greg is co-founder of three
companies, including PictureTel Corp.
Wednesday: Gert Smolka, "The Oz Programming Model"
++++++++++++++++++++++++++++++++++++++++++++++++++
The Oz Programming Model (OPM) is a concurrent programming model that subsumes
functional and object-oriented programming as facets of a general model. This
is particularly interesting for concurrent object-oriented programming, for
which no comprehensive and formal model existed until now. There is a
conservative extension of OPM providing the problem-solving capabilities of
constraint logic programming. OPM has been developed together with a
concomitant programming language Oz designed for applications that require
complex symbolic representations, organization into multiple agents, and soft
real-time control. An efficient, robust, and interactive implementation of Oz
is freely available.
Gert Smolka is Professor of Computer Science at the Universit\"at des
Saarlandes at Saarbr\"ucken and head of the Programming Systems Lab of the
DFKI. He received his Dr. rer. nat. in Computer Science in 1989 from the
Universit\"at Kaiserslautern. He is a member of the executive committee of
the European Network of Excellence in Computational Logic and served in many
international programming committees.
Gert Smolka has published papers on computational logic, logic programming,
type systems, knowledge representation and reasoning, formalisms for
computational linguistics, constraints, concurrency, and programming languages
and systems. Since 1991, Gert Smolka is leading the design and implementation
of Oz, the first concurrent language combining a rich object system with
advanced features for symbolic processing and problem solving. He and his
group have now begun work towards a distributed version of Oz supporting the
construction of open systems.
Thursday: Bjorn Engquist, "Parallelism in Computational Algorithms and
++++++++++++++++++++++++ the Physical World"
Most processes in the real world are local and contain a high degree of
parallelism. A simple example is weather prediction. The weather at any
location depends on the weather at earlier times in the neighborhood. The
computational algorithms should map these processes efficiently onto the
current parallel architecture. Many modern computational methods are
hierarchial and contain some global interconnection even if the underlying
process is local. The overall efficiency depends on how well this connectivity
is supported by the architecture. Different classes of modern methods in
scientific computing and their parallel implementation will be discussed.
Bjorn Engquist is Professor in Numerical Analysis at the Royal Institute of
Technology, Stockholm and the University of California, Los Angeles. He
recieved his PhD from Uppsala University 1975 and was Professor there 1981-85.
He has written two books and more than fifty research papers in the fields of
Scientific Computing and Numerical Analysis. In particular he has worked on
the numerical simulation of differential equations with applications in fluid
mechanics and electro mechanics. He was the first recipient of the SIAM award
in Scientific Computing 1982 and a Guggenheim Fellow 1992. Presently he is the
Director of the Center of Excellence PSCI and the Center for Parallel
Computers at the Royal Institute of Technology.
3 PRELIMINARY PROGRAM - PAPER SESSIONS
=======================================
Language Implementation I
+++++++++++++++++++++++++
Tuesday August 29th, 10:30 - 12:30
"Execution Of Distributed Reactive Systems"
Alain Girault and Paul Caspi
"Relating Data-Parallelism and (And-) Parallelism in Logic Programs"
Manuel V. Hermenegildo and Manuel Carro
"On the Duality Between Or-parallelism and And-parallelism in Logic
Programming"
Enrico Pontelli and Gopal Gupta
"Functional Skeletons for Parallel Coordination"
John Darlington, Yi-ke Guo, Hing Wing To, Jin Yang
Architecture Design
+++++++++++++++++++
Tuesday August 29th, 10:30 - 12:30
"On the Scalability of Demand-Driven Parallel Systems"
Ronald C. Unrau, Michael Stumm and Orran Krieger
"Bounds on Memory Bandwidth in Streamed Computations"
Sally A. McKee, Wm. A. Wulf, and Trevor C. Landon
"StarT-NG: Delivering Seamless Parallel Computing"
Derek Chiou, Boon S. Ang, Arvind, Michael J. Beckerle, Andy Boughton, Robert
Greiner, James E. Hicks and James C. Hoe
"Costs and Benefits of Multithreading with Off-the-Shelf RISC Processors"
Olivier C. Maquelin, Herbert H.J. and Hum Guang R. Gao
Semantics and tools
+++++++++++++++++++
Tuesday August 29th, 14:00 - 16:00
"Transformation techniques in Pei"
S. Genaud, E. Violard, and G.-R. Perrin
"On the completeness of a proof system for a simple data-parallel programming
language"
Luc Bouge, David Cachera
"An Implementation of Race Detection and Deterministic Replay with MPI"
C. Cl\'emen\c{c}on, J. Fritscher, M.J. Meehan and R. R\"uhl
"Formal and experimental validation of a low overhead execution replay
mechanism"
Alain Fagot and Jacques Chassin de Kergommeaux
Interconnection Networks I
++++++++++++++++++++++++++
Tuesday August 29th, 14:00 - 16:00
"On Efficient Embedding of Grids into Grids in PARIX"
T. Roemke, M. Roettger, U.-P. Schroeder, J. Simon
"Optimal Emulation Of Meshes On Meshes-of-Trees"
Alf-Christian Achilles
"Optimal Embeddings In The Hamming Cube Networks"
Sajal K. Das and Aisheng Mao
"Hierarchical Adaptive Routing Under Hybrid Traffic Load"
Ziqiang Liu
Parallel Algorithms I
+++++++++++++++++++++
Tuesday August 29th, 16:30 - 18:00
"Tight Bounds on Parallel List Marking"
Sandeep N. Bhatt, Gianfranco Bilardi,Kieran T. Herley, Geppino Pucci and
Abhiram G. Ranade
"Optimization of PRAM-Programs with Input-Dependent Memory Access"
Welf Loewe
"Optimal Circular Arc Representations"
Lin Chen
Cache Systems
+++++++++++++
Tuesday August 29th, 16:30 - 18:00
"Exploiting Parallelism in Cache Coherency Protocol Engines"
Andreas Nowatzyk, Gunes Aybay, Michael Browne, Edmund Kelly, Michael Parkin,
Bill Radke and Sanjay Vishin
"Correctness of S3-mp - A Case Study of Distributed Directory-based Cache
Coherence Protocol"
Fong Pong, Andreas Nowatzyk, Gunes Aybay and Michel Dubois
"Efficient Software Data Prefetching for a Loop with Large Arrays"
Se-Jin Hwang, Myong-Soon Park
Loop Parallelization
++++++++++++++++++++
Wednesday August 30th, 10:30 - 12:00
"Generation of synchronous code for automatic parallelization of while loops"
Martin Griebl and Jean-Francois Collard
"On Explicit Computation Movement"
Dattatraya Kulkarni and Michael Stumm
"Synchronization Migration for Performance Enhancement in a Doacross Loop"
Rong-Yuh Hwang
"An Array Partitioning Analysis for Parallel Loop Distribution"
Marc Le Fur, Francoise Andre' and Jean-Louis Pazat
Load Balancing and Parallel Algorithms II
+++++++++++++++++++++++++++++++++++++++++
Wednesday August 30th, 10:30 - 12:00
"A Model for Efficient Programming of Dynamic Applications on Distributed
Memory Multiprocessors"
Andreas Erzmann
"Efficient Solutions for mapping parallel programs"
P. Bouvry J. Chassin and D. Trystram
"Optimal Data Distributions for LU Decomposition"
Thomas Rauber and Gudula Runger
"Detecting Quantified Global Predicates in Parallel Programs"
Mark Minas
Compiling Techniques
++++++++++++++++++++
Wednesday August 30th, 14:00 - 16:00
"Using Knowledge-Based Techniques for Parallelization on Parallelizing
Compilers"
Chao-Tung Yang, Shian-Shyong Tseng, Cheng-Der Chuang, and Wen-Chung Shih
"Automatic vectorization of communications for data-parallel programs"
Cecile Germain and Franck Delaplace
"The Program Compaction Revisited: the Functional Framework"
Marc Pouzet
"Featherweight Threads and ANDF Compilation of Concurrency"
Ben Sloman and Tom Lake
Applications
++++++++++++
Wednesday August 30th, 14:00 - 16:00
"Parallel N-Body Simulation on a Large-Scale Homogeneous Distributed System",
John Romein and Henri Bal
"Analysis of Parallel Scan Processing in Shared Disk Database Systems",
Erhard Rahm and Thomas Stoehr
"Polynomial Time Scheduling of Low Level Computer Vision Algorithms on
Networks of Heterogeneous Machines",
Adam R. Nolan and Bryan Everding
"Mapping Neural Network Back-Propagation onto Parallel Computers with
Computation/Communication Overlapping",
Bernard Girau
Language Implementation II
++++++++++++++++++++++++++
Thursday August 31st, 10:30 - 12:00
"Super Monaco: Its Portable and Efficient Parallel Runtime System"
J. Larson, B. Massey and E. Tick
"Quiescence Detection in a Distributed KLIC Implementation"
Kazuaki Rokusawa, Akihiko Nakase, Takashi Chikayama
"Compiler optimizations in Reform Prolog: experiments on the KSR-1
multiprocessor"
Thomas Lindgren, Johan Bevemyr and Hakan Millroth
Interconnection Networks II
+++++++++++++++++++++++++++
Thursday August 31st, 10:30 - 12:00
"Bidirectional Ring: An Alternative to the Hierarchy of Unidirectional Rings"
Muhammad Jaseemuddin and Zvonko G. Vranesic
"A Formal Study Of The Mcube Interconnection Network"
Nitin K. Singhvi and Kanad Ghose
"Multiwave Interconnection Networks for MCM-Based Parallel Processing"
Shinichi Shionoya, Takafumi Aoki and Tatsuo Higuchi
Scheduling
++++++++++
Thursday August 31st, 13:30 - 15:00
"Scheduling Master-Slave Multiprocessor Systems"
Sartaj Sahni
"Time Space Sharing Scheduling: A Simulation Analysis"
Atsushi Hori, Yutaka Ishikawa, Jorg Nolte, Hiroki Konaka, Munenori Maeda,
Takashi Tomokiyo
"Agency Scheduling - A Model for Dynamic Task Scheduling"
Johann Rost, Franz-Josef Markus and Yan-Hua Li
Fault Tolerance and SIMD Arrays
+++++++++++++++++++++++++++++++
Thursday August 31st, 13:30 - 15:00
"FFTs on a linear SIMD array"
Mattias Johannesson
"Tolerating Faults in Injured Hypercube Using Maximal Fault-Free Subcube-Ring"
Jang-Ping Sheu and Yuh-Shyan Chen
"Communication in Multicomputers with Nonconvex Faults"
Suresh Chalasani and Rajendra V. Boppana
4 POSTER SESSION
=================
The poster session will be held Wednesday, August 30th, 14:00 - 16:00.
"Parallelising Programs with Algebraic Programming Tools"
A.E. Doroshenko and A.B. Godlevsky
"Parallel Prolog with Uncertainty Handling"
Katalin Molnar
"A Special-Purpose Computer Architecture for Qualitative Simulation"
Marco Platzner and Bernhard Rinner
"Portable Software Tools for Parallel Architectures"
Barnes and C Wadsworth
"Boosting the Performance of Workstations through WARPmemory"
Christoph Siegelin
"A Monitoring System for Heterogeneous Distributed Environments"
Aleksander Laurentowski, Jakub Szymaszek, Andrzej Uszok, Krzysztof Zielinski
"A Metacircular Data-Parallel Functional Language"
Gaetan Hains and John Mullins
"Efficient Run-Time Program Allocation on a Parallel Coprocessor"
Jurij Silc and Borut Robic
"A Program Manipulation System for Fine-Grained Architectures"
Vladimir A. Evstigneev, Victor N. Kasyanov
"Real-Time Image Compression Using Data-Parallelism"
P. Moravie, H. Essafi, C. Lambert-Nebout, and J-L. Basille
"Congestion Control in Wormhole Networks: First Results"
Abdel-Halim Smai
5 VENDOR SESSION
=================
There will be a vendor session during EURO-PAR'95. If you are interested in
exhibiting, please contact Bjorn Lisper (lisper@it.kth.se) to receive the
vendor information package.
The vendor session is preliminarily scheduled for 10:30 - 12:30, on Wednesday,
August 30th.
6 PROCEEDINGS ON THE WWW
=========================
Together with Springer-Verlag, EURO-PAR'95 is running a pilot project to put
the proceedings on-line prior to the conference. Titles and abstracts will be
in WWW format, and postscript files of (most) papers can be downloaded. Only
registered participants of the conference will have access to the full papers.
Titles, abstracts, and additional author-provided information is publicly
readable.
7 TUTORIALS
============
All tutorials will be held on Monday, 28th August.
Tutorial 1 (full day): Per Stenstrom
"Multiprocessors and Multicomputers - Programming
and Design"
Tutorial 2 (half day): Chris Jesshope
"Scalable Parallel Computers"
Tutorial 3 (half day): Richard Hofmann
"ZM4/SIMPLE: a Universal Hardware and Trace Evaluation
Package for Parallel and Distributed Systems"
Tutorial 4 (half day): Erland Fristedt and Per Oster
"Parallel Applications"
Tutorial 5 (half day): Kam-Fai Wong
"Parallel Database Systems Engineering"
Tutorials cost 1400 SEK for a full-day, and 800 SEK for half-day. For students
the prices are 600 and 400, respectively. Late registration (after 30th of
June) is charged with an extra 20%. Prices include Swedish value-added tax.
Tutorial 1
++++++++++
"Multiprocessors and Multicomputers - Programming and Design"
Per Stenstrom
We cover in this tutorial an emerging class of high-performance computer
systems known as MIMD systems. These systems are built from commodity
microprocessors that cooperate in solving various compute-intensive
applications from numerical algorithms to industrial-oriented control
algorithms in embedded systems. Two distinct classes of systems are
considered: shared-memory multiprocessors and multicomputers where messages
are used to coordinate the parallel computation.
The tutorial is divided into two parts that address programming as well as
design of multiprocessors and multicomputers. Regarding programming, we start
from traditional imperative programming languages such as C and study how we
can extend them with constructs to define and coordinate parallel actions. We
then study how problem partitioning affects the algorithmic speedup of a
computation.
Regarding the design part of the tutorial, we first focus on design principles
and performance issues for interconnection networks (INs)--an important part
of any parallel computer. We specifically study how IN topologies and routing
algorithms affect the cost, latency, and bandwidth of a parallel computer.
While multiprocessors and multicomputers both rely on efficient message
transfers, shared-memory multiprocessors must support automatic data
replication across processing nodes to be effective. A key mechanism to
achieve this goal is to use caching and we focus in detail on design
principles as well as performance issues of coherent caches--hardware-based
schemes to support data replication in shared-memory multiprocessors. Finally,
we look at advanced schemes for tolerating long latencies in large-scale
machines such as prefetching, memory consistency model relaxation, and
multithreading.
The tutorial is mainly targeted to practitioners in the field of computer
engineering, but also to researchers in computer science who are interested in
the state-of-the-art of parallel computer architecture. The tutorial assumes
basic knowledge in programming and computer organization and architecture.
Per Stenstrom is an Associate Professor of Computer Engineering at Lund
University, where he has conducted research in parallel processing since 1984.
He received an MS degree in electrical engineering in 1981 and a PhD degree in
computer engineering in 1990, both from Lund University. His primary research
interests are in parallel architectures, performance evaluation, and memory
systems for high-speed computer systems and he has authored and co-authored
more than 40 papers in these areas. He is also an author of two textbooks on
computer organization and architecture.
Besides his activities in Lund, Dr. Stenstrom is a research advisor at Swedish
Institute of Computer Science. He has been a visiting scientist at Carnegie
Mellon University (1987), Stanford University (1991), and University of
Southern California (1993), where he has studied various aspects of
shared-memory multiprocessor architectures. He is on the editorial board of
the Journal of Parallel and Distributed Computing and a member of the ACM, the
IEEE, and the Computer Society.
Tutorial 2
++++++++++
"Scalable Parallel Computers"
Chris Jesshope
This tutorial provides an up-to-date overview of architecture and languages
for scalable parallel computers. It focusses on distributed memory
multi-processors and data-parallel languages. It is just about agreed now that
scalability in architectural terms can not be considered in isolation, we must
also have programming methodologies which are scalable and portable. It will
be argued that these require a single global address space which will develop
the seminar along the axis of virtual or distributed shared memory systems.
Such memory systems however, are nun-uniform in their access properties (NUMA
architectures). Therefore a large proportion of the time will be spent
studying how within such architectures we can first of all reduce latency and
secondly how we can tolerate any remaining latency. These issues will lead us
to study networks for parallel computers and also scheduling mechanisms and
other latency hiding techniques. The seminar will span on the architectural
side cache-based processors, multi-threaded processors and dataflow
processors, while on the language side it will consider EVAL, F-code, FORTRAN
90 and HPF.
Target audience is anyone who is interested in recent developments in scalable
parallel computer architectures. This is not basic material, it presents a
coherent view of the fundamental problems of reaching this goal and some of
the developments which have been seen in recent commercial architectures as
well as developments from recent research which show promise in achieving this
goal. It does not however require a detailed knowledge of parallel computer
systems. Some background knowledge in conventional computer architecture is
however required (e.g. 1st degree level).
Chris Jesshope is Racal Professor of IT at the University of Surrey, where he
leads the Computer Systems Research Group. He has had a reserach interest in
parallel computers since 1976, when he was a research fellow at Reading
University and a user of the ICL DAP, and Illiac V, both SIMD computers. Since
then his interests have moved more towards architecture and implementation of
parallel machines. At Southampton University 1981-1990 he has led projects
implementing reconfigurable parallel computers, both SIMD and MIMD computers.
At the University of Surrey, since 1990, he has led projects in which asics
have been designed and fabricated to give low-latency, high-performance
communication networks for scalable parallel computers. In addition to that
he has established several projects whose aim is to provide portable software
tools for programming parallel computers, based on the automatic compilation
of un-annotated, data-parallel langages.
Chris Jesshope has published in excess of 100 papers in and has edited several
state-of-the-art reports in this area. He is a co-author of a very successful
book on parallel computers, which has been published in 5 editions, including
two in English, one in Russian, one in Japanese and one in Romanian. He has
given numerous invited papers at international conferences in more than 15
countries. He is the Honorary Editor of the IEE Proceedings Part E, Computers
and Digital Techniques, Series Editor for the Chapman and Hall book series in
Parallel and Distributed Computing, as well as being on a number of editorial
boards for other journals in this area.
Chris Jesshope is Chairman of the Steering committee for EUROPAR, a member of
the IEE, a Chartered Engineer and a Fellow of the British Computer Society.
Tutorial 3
++++++++++
"ZM4/SIMPLE: a Universal Hardware Monitor and Trace EvaluationPackage for
Parallel and Distributed Systems"
Richard Hofmann
University Erlangen, IMMD VII
Martensstr. 3, D-91058
Erlangen
phone: +49-9131-85-7026
email: rhofmann@informatik.uni-erlangen.de
Target audience:
* persons involved in programming of parallel and distributed systems,
with common knowledge in computer science and practice in parallel
and distributed processing
Due to the complex interactions between activities in parallel processes, the
dynamic behavior of the system cannot be quantified a priori. However, a
profound knowledge about what is going on in the system is the basis for
balancing the load in order to optimally utilize the potential power of such a
parallel system. Monitoring is a valuable aid in getting the necessary insight
into this dynamic behavior of interacting processes. In this tutorial, the
universal distributed hardware monitor system ZM4 as well as the universal
toolbox for event trace evaluation SIMPLE is discussed. Both toolsets are in
practical use by a number of research institutes at universities and in the
industry as well as by ourselves.
In the first part of the tutorial, the principles of measurement-based
performance analysis in parallel and distributed systems are briefly sketched.
It is shown that an external hardware monitor system can be used for any
parallel and distributed system, provided that it has the necessary features.
These features are 1) a global timebase with sufficient accuracy, 2) a
scaleable architecture, and 3) a universal interfacing scheme that makes it
easily adaptable to arbitrary object systems. In the sequel, ZM4, a universal
distributed monitor system providing these features is introduced. ZM4's
relevance for parallel applications is shown by discussing monitoring projects
in state of the art parallel and distributed systems.
The second part of the tutorial deals with SIMPLE (Source related Integrated
performance Measurement and modeLing Environment), a universal and powerful
toolbox for all tasks related to the process of presenting the meaning of
trace data to human beings. In a similar way as ZM4, SIMPLE is universal in
the following sense: SIMPLE can be used for arbitrary evnet traces, regardless
of their source, structure, meaning, and content. In order to achieve this,
SIMPLE follows a layered approach with a configurable access layer to the
actual trace data. The SIMPLE toolbox contains statistics-oriented tools like
trcstat (compute common trace statistics), fact (find activities), and varus
(validating rules checking system) as well as interactive graphics-oriented
tools like gantt (draw state time diagrams) and hasse (draw causality diagrams
between process traces). All these tools will be introduced with examples from
measurements at practical parallel and distributed systems.
Richard Hofmann studied at the University of Erlangen, where he received his
diploma in electrical engineering. After joining the IMMD (Institute for
mathematical machines and data processing) at the same university, he designed
and implemented the universal distributed monitor system ZM4. In 1992 he
received the Dr.-Ing degree in computer science with his work on Secure
Temporal Relationships for Performance Analysis in Parallel and Distributed
Systems. For this work he received the best dissertation award from the
section communication and distributed systems in the GI/ITG. In 1991, Dr.
Hofmann lectured on hardware and hybrid monitoring in parallel and distributed
systems at FUDAN university inShanghai in China.
His current research interests include hardware monitoring, hybrid monitoring,
hardware design for monitor interfaces, trace evaluation and tools, clock
synchronization, basic problems in parallel and distributed systems,
programmable logic devices.
Tutorial 4
++++++++++
"Parallel Applications"
Erland Fristedt Dr. Per \"Oster
Center for Parallel Computers Center for Parallel Computers
Royal Institute of Technology Royal Institute of Technology
100 44 Stockholm 100 44 Stockholm
Sweden Sweden
Email: erlandf@pdc.kth.se Email: per@pdc.kth.se
Tel: +46 8 790 6907 Tel: +46 8 790 6261
Fax: +46 8 24 77 84 Fax: +46 8 24 77 84
A substantial part of existing standard computational codes in industry and
science are today available in versions for scalable parallel computers.
Although some of these implementations show a lack of efficiency and are only
partial parallelizations the present interest from software vendors must be
considered a commercial brake trough for parallel technology.
We will in this tutorial discuss and give an introduction to some aspects of
development of parallel applications such as, communication models, data
decomposition, load-balancing and use of message-passing libraries.
Target audience:
* Everyone interested in an introduction to parallel
applications.
Erland Fristedt has a Master in Computer Science from KTH, Sweden. He has
several years of experience in development of parallel applications for
message passing systems at the Swedish National Research Defense
Establishment. At present he is working with parallel applications at the
Center for Parallel Computer at KTH, Sweden.
Per \"Oster has a BSc in Physics from University of Uppsala, Sweden and a PhD
in Theoretical Atomic Physics from Chalmers University of Technology, Sweden.
He has four years of experience as consultant in applied mathematics and
responsible for engineering applications in the Volvo Data Corporation. At
present he is working with parallel applications at the Center for Parallel
Computer at KTH, Sweden.
Tutorial 5
++++++++++
"Parallel Database Systems Engineering"
Dr. Kam-Fai Wong
Department of Systems Engineering & Engineering Management,
Chinese University
Shatin, N.Y.
Hong Kong.
Email - kfwong@se.cuhk.hk
Tel: +852 6098332
Fax: +852 6035505
Today, very large databases may easily involve over tera-bytes of data. This
trend shows no sign of diminishing. Albeit the advancements in processor
technology, handling such large volume of information is becoming increasingly
difficult for conventional database management systems which run on sequential
computers. To overcome this predicament, a number of research projects are
investigating the use of parallel computers. The inherent parallelisms behind
its data model (e.g. relational) render database suitable for parallel
implementation. In this tutorial, the concept of parallel database systems
(PDS) which is based on the extended dataflow computation model will be
presented. In addition, few engineering issues regarding to the implemen-
tation of the model will be reviewed.
Target Audience:
* Database developers who are interested in parallel implementations
* Parallel software developers who are planning to develop a database system
* First year Postgraduate students in database or parallel computing
Kam-Fai Wong obtained his PhD from the University of Edinburgh, Scotland, in
1987, in the area of computer architectures. After his PhD, he has
performed research in Heriot-Watt University (Edinburgh, Scotland), UniSys
(Livingston, Scotland) and ECRC (Munich, Germany). At present he is a Project
Coordinator at the Chinese University of Hong Kong, in charge of the IPOC
(Intelligent Processing Of Chinese) project. His research interests are
parallel database and information systems. He has published over 25 technical
papers in these areas in various international journals, conferences and
books.
During his 8 years postdoctoral research period, he has given many seminars.
In 1993/95, he is one of the ACM lecturers worldwide. He is a member of
IEEE-CS, ACM and IEE(UK) and have served as the AI/DB track chair in 1994 ACM
Symposium on Applied Computing, the Asian Coordinator of the 1994 Parallel and
Distributed Information Systems and PC members of TOOLS94, PARLE94, VLDB94,
SPDP94, ICDCS95, DASFAA95, Europar95 and ICDE96.
8 STEERING COMMITTEE
=====================
Chris Jesshope, Chairman (UK)
Kiril Boyanov (Bulgaria)
Agnes Bradier (European Union)
Michel Cosnard (France)
Lucio Grandinetti (Italy)
Constantine Halatsis (Greece)
Seif Haridi (Sweden)
Ron Perrott (UK)
Ivan Plander (Slovakia/UK)
Dieter Reinartz (Germany)
Mateo Valero (Spain)
Richard Wait (UK)
Pierre Wolper (Belgium)
9 PROGRAMME COMMITTEE
======================
Emile H. L. Aarts (Netherlands) Yasunori Kimura (Japan)
Gul Agha (USA) Manolis Katevenis (Greece)
Khayri Ali (Sweden) Ramamohanarao Kotagiri (Australia)
Makoto Amamiya (Japan) Bjorn Lisper (Sweden)
Francoise Andre (France) Peter Magnusson (Sweden)
B. Bergsten (France) Dimitris Maritsas (Greece)
M. Boari (Italy) Andrei Massalovitch (Russia)
Luc Bouge (France) Moray McLaren (UK)
Kiril Boyanov (Bulgaria) Burkhard Monien (Germany)
John Carter (USA) Hiroshi Nakashima (Japan)
Takashi Chikayama (Japan) Rishiyur S. Nikhil (USA)
Andrzej Ciepielewski (Sweden) Ron Perrott (UK)
Michel Cosnard (France) Ivan Plander (Slovakia)
Doug DeGroot (USA) Michael Reeve (Belgium)
Michel Dubois (USA) Karl-Dieter Reinartz (Germany)
Paul Feautrier (France) Dirk Roose (Belgium)
Robert Fowler (Denmark) Shuichi Sakai (Japan)
Guang R. Gao (Canada) Joel Saltz (USA)
Geoffrey C. Fox (USA) Paul Spirakis (Greece)
Wolfgang Gentzsch (Germany) Per Stenstrom (Sweden)
Lucio Grandinetti (Italy) Ondrej Sykora (Slovakia)
Pascal Gribomont (Belgium) Peter Szeredi (Hungary)
Erik Hagersten (USA) Kazuo Taki (Japan)
Constantine Halatsis (Greece) Sergios Theodoridis (Greece)
Seif Haridi (Sweden) Lars-Erik Thorelli (Sweden)
M. Hatzopoulos (Greece) Evan Tick (USA)
M. Hermenegildo (Spain) Marian Vajtersic (Slovakia)
P.A.J. Hilbers (Netherlands) Mateo Valero (Spain)
Ladislav Hluchy (Slovakia) Valentin Voevodin (Russia)
Chris Jesshope (UK) R. Wait (UK)
Peter Kacsuk (Hungary) David H.D. Warren (UK)
Kam-Fai Wong (Hong Kong)
10 ORGANIZING COMMITTEE
========================
Conference Chair Lars-Erik Thorelli (Sweden)
Programme Chair Seif Haridi (Sweden)
Programme Co-Chair Khayri Ali (Sweden)
Japan & Asia Coordinator Makoto Amamiya (Japan)
North and South American Coordinator Doug DeGroot (USA)
Exhibition Chair Bjorn Lisper (Sweden)
Workshop Chair Peter Magnusson (Sweden)
European Union Liaison Michael Reeve (EU)
Central & East European Coordinator Valentin Voevodin (Russia)
Local Arrangements Abdel-Halim Smai (Sweden)
Treasurer Eva Skarback (Sweden)
11 WORKSHOP SHARED-MEMORY MULTIPROCESSORS
==========================================
A one-day workshop on shared-memory multiprocessors will be held in
conjunction with the EURO-PAR'95 conference in Stockholm on August 27th. The
aim of the workshop is to bring together researchers active in the field of
shared-memory multiprocessing to debate work in progress.
Topics of interest include, but are not limited to:
* Hardware/software tradeoffs in supporting a shared-memory model
* Updates on implementation projects in industry and academia
* Tools and methodologies for performance tuning
* Compiler optimization techniques
* Emerging applications
* New architecture proposals and evaluations
* Hybrid architectures supporting shared-memory and message passing
* Performance evaluation
* Programmability issues
Participants are encouraged to submit an abstract of about 500 words
before July 15 to the workshop organizers. Contributions will be
reviewed by the workshop organizers and important selection criteria
are relevance and topic balance. The final program will be decided
on August 1.
Important dates:
* July 15, Submission deadline
* August 1, Notification to participants
* August 27, Workshop day
* August 29-31, The Conference
Registration for the workshop is 450 SEK, for students 250 SEK. The fee covers
coffee, lunch, dinner, and proceedings.
The workshop is organized by:
Anders Landin (landin@sics.se)
Per Stenstrom (per@dit.lth.se)
12 REGISTRATION FEES AND PAYMENT
=================================
Early registration is 3400 SEK (including 680 SEK value added tax). For
students, there is a 50% reduction. Deadline for early registration is end of
July. If you register as student you must furnish an official letter to that
effect from your University. (Currently, 7.3 SEK is 1 USD)
Late registration is 3800 SEK, for students 1900 SEK.
Registration fee includes coffee breaks, lunches, reception, and dinner as
listed in the preliminary programme above. It also includes one copy of the
proceedings. Student price does not include lunches, reception, banquet, or
proceedings.
Payment can be done either by sending a check to:
Swedish Institute of Computer Science
Box 1263
S-164 28 KISTA
Sweden
(Do *not* write EURO-PAR on the check)
or, preferably, you can pay via Eurogiro or SWIFT to the KTH (Royal Institute
of Technology) account number:
1 56 53 - 9
with Postgirot Bank, S-105 06 Stockholm, Sweden.
SWIFT address: PGSI SESS
Don't forget to include your full name on the Eurogiro/SWIFT order.
For various reasons we cannot accept credit card payments.
Also, please "cut" and fill in the following form and e-mail it to
"europar95registration@sics.se".
If you do not have access to e-mail and have recieved this in hardcopy, you
can fax the same information to +46 8 751 72 30.
----------------------------- Cut here -----------------------------------
============= BEGIN REGISTRATION INFORMATION (include this line) =============
(Fill in carefully. Do not use for more than one person. Do not erase
any text from the form.)
FIRST NAME:
LAST NAME:
AFFILIATION:
(University or company.)
E-MAIL ADDRESS:
(If you send this information to us electronically, we will parse the "From:"
field. If you fax us this information, then please include your e-mail
address.)
CONTACT INFORMATION:
(Information on how to contact you, such as office phone numbers, fax number,
pager, etc. This information will be kept strictly confidential by the
organizing committee and will be used to contact you if e-mail fails.)
MAILING ADDRESS:
(Your full (postal) mailing address.)
STUDENT:
("Yes" or "No". Note that if you claim student status then we must receive,
prior to the conference, an offical *hardcopy* (i.e. physical) letter to this
effect on university letterhead.)
ACTIVITIES:
(Write an "X" in the boxes for each activity for which you wish to register.)
Registration Fee (in SEK)
Full Student
Workshop (one day): [] 450 250
Tutorial 1 (full day): [] 1450 600
Tutorial 2 (half day): [] 800 400
Tutorial 3 (half day): [] 800 400
Tutorial 4 (half day): [] 800 400
Tutorial 5 (half day): [] 800 400
Conference (three days): [] 3400 1700
(Registration after July 31st is 20% extra, except conference registration
which is 3800 SEK, 1900 SEK for students.)
TOTAL FEE:
(Calculate your total fee and write it here.)
PAYMENT METHOD:
(Here write "check" or "SWIFT", depending on how you are paying.)
PUBLIC INFORMATION:
(Please write the information you wish included in the "list of participants"
that will be distributed at the conference. Do not write more than 5 lines.
For example, you might want your name, university, and e-mail address to be
listed. You may of course leave this section blank, in which case we will not
publicize your attendance.)
+++++++++++++ END REGISTRATION INFORMATION (include this line) +++++++++++++
----------------------------- Cut here -----------------------------------
13 HOTEL INFORMATION
=====================
We have reserved rooms for EURO-PAR'95 participants at the following hotels.
Our preliminary reservations will be held until the 28th of July. Please
reserve rooms as early as possible, as there are at least two other major
conferences in Stockholm at the same time as EURO-PAR'95.
Note that sharing rooms in Sweden does not necessarily save you much money.
However, if you wish help in finding someone to share a room with, send an
e-mail to "europar95registration@sics.se".
For help with finding other accomodations than the ones below, you can contact
the accomodation booking office, at tel. +46 8 240880, fax +46 8 7918666.
Ersta Gasthem Tel: +46 8 714 63 41
Erstag 1 Fax: +46 8 714 63 51
S-116 28 STOCKHOLM Single: 390-530 SEK
Situated in southern part of city, close to buses and underground.
Memory Hotel Tel: +46 8 793 07 00
Borgarfjordsgatan 5 Fax: +46 8 793 08 00
Box 1092
164 21 KISTA Single: 918 SEK
Situated in Kista, very close to the conference. Boring area on weekends.
Reservation number for EURO-PAR is "BK488".
Mr Chip Hotel Tel: +46 8 750 56 00
Farogatan 9 Fax: +46 8 751 85 80
Box 1196
164 22 KISTA Single: 870 SEK
Situated in Kista, very close to the conference. Boring area on weekends.
Reservation number for EURO-PAR is "BR667".
City Backpackers Vandrarhem Tel: +46 8 20 69 20
Barnhusg 16 Fax: +46 8 20 69 20
S-111 23 STOCKHOLM Bed: 125-150 SEK
Located downtown, close to all transportations. You will (probably) share the
room with somebody else.
Hotell Oden Tel: +46 8 349 340
Karlbergsv 24 Fax: +46 8 32 22 99
Box 6246
S-102 34 STOCKHOLM Single: 825 SEK
Central located close to underground.
Welcome Hotel Tel: +46 8 760 25 20
Notarievagen 5 Fax: +46 8 36 52 45
S-175 63 JARFALLA Single: 645 SEK
Direct buses to Kista.
(The above prices may change without notice. Please confirm them when you book
your room. If you have any problems with the above hotels, or if any of the
above information is incorrect, please let us know. Unfortuntately, we do not
have the manpower to assist you with your reservations.)
14 TOURIST INFORMATION
=======================
Stockholm is the political and economical capital of Sweden. Originally,
Stockholm was built on 14 islands where Lake Maelaren meets the Baltic Sea.
Water covers one third of the city area. Bridges, quays and locks join the
city districts of Gamla Stan, Norrmalm, Oestermalm, Vasastan, Kungsholmen and
Djurgaarden. The water in Stockholm is so clean that salmon can be caught
right in the middle of the city, just a few minutes walk from the city centre.
The official, written history of Stockholm begins 700 years ago, but there are
many rune-stones and other traces of the Vikings to be found.
In case you're considering a Scandinavian vacation, note that the Stockholm
Water Festival is August 11-20. For 10 summer days, the entire city center is
closed to traffic, making room for 1200 events ranging from rock to rugby,
fireworks to freestyle jumping, and symphony to street theater. With well over
3 million visitordays logged each year, the Stockholm Water Festival is
Europe's largest tourist event. The program includes the World Fireworks
Championship. The Festival has become a highlight of the Swedish summer: one
of three Swedes have been to at least one festival since 1991!
Weather in August is warm, with light, balmy evenings and the odd shower.
For tourist information about Stockholm, contact Stockholm Information
Services on tel +46 8 7892495 or fax +46 8 7892491.
The conference will be held in Electrum, Kista, on the northern edge of
Stockholm (about 20 minutes by car or train). Electrum is the leading Swedish
competence center for active cooperation between education, research and
industry in the information technology area. It was founded in 1988 and now
2000 people work in the immediate vicinity, of which approximately 400 are
teachers or scientists. There are also about 2000 students in the building.
15 EURO-PAR'96
===============
EURO-PAR'96 will be held at ENS-Lyon, France, August 27-29, 1996):
General Chair Pierre Fraigniaud
Programme Chairs Luc Bouge and Yves Robert
Organization Chair Anne Mignotte
For more information, see our web server.
16 CONTACT INFORMATION
=======================
Official Mailing Address
EURO-PAR'95
SICS
Box 1263 (visit/delivery: Isafjordsgatan 22)
S-164 28 Kista
Sweden
Phone: +46 8 752 15 00
Fax: +46 8 751 72 30
E-mail: europar95@sics.se
Infobahn Ramps
WWW page: http://www.sics.se/europar95
ftp site: sics.se:europar95
Mailing addresses:
europar95info@sics.se - send empty mail to be added to our
mailing list (low bandwidth)
europar95registration@sics.se - to register for the conference, or other
related matters such as hotels, trains, etc
europar95papers@sics.se - if you're an author, questions related to
your paper
europar95@sics.se - all other questions
--
Peter Magnusson
psm@sics.se http://www.sics.se/~psm
Swedish Institute of Computer Science
--
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