Call for Participation: PACT'95 (Andrew Sohn)
Tue, 18 Apr 1995 17:17:27 GMT

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Call for Participation: PACT'95 (1995-04-18)
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Newsgroups: comp.arch,comp.parallel,comp.compilers
From: (Andrew Sohn)
Keywords: conference, CFP, parallel, architecture
Organization: New Jersey Institute of Technology
Date: Tue, 18 Apr 1995 17:17:27 GMT

International Conference on Parallel Architectures and Compilation Techniques
                        June 26-29, 1995, Limassol Sheraton, Limassol, Cyprus

Sponsored by IFIP WG 10.3, ACM SIGARCH, and IEEE TC on Computer Architecture.

Cyprus lies between three continents: Europe, Asia and Africa. It is a
safe and enjoyable tourist destination. Last year, more than 2 million
tourists visited the island that has a population of only half a million
people. English is the second language of Cyprus and is spoken
virtually by everyone in the tourist and commercial community. The
traffic and street signs are in both Greek and English. Cyprus is a
cosmopolitan island with 9000 years of history. More than 30 airlines
and a good number of shipping lines connect Cyprus with the rest of the
world. For complete information on visiting Cyprus, you may consult
the Cyprus Home Page on WWW (

More information on conference program, tutorial, registration, etc.
can be obtained from WWW,,,
or by sending E-mail to pact95@enee.

The International Symposium on Computer Architecture will take place
in Santa Margherita Ligure, Italy, June 22-24, 1995 (just before
PACT'95). The International Conf. on Supercomputing will take place
immediately after PACT'95 in Barcelona, Spain, July 3-7, 1995. Special
air fares are being negotiated to allow participants to attend all meetings.

o Instruction-Level Parallelism, Yale Patt, Univ. of Michigan
o New Paradigms for ILP, Jim Smith, Univ. of Wisconsin
o Trends in Compiler Technology for Parallel Computers, David Padua, UIUC

o Front-end parallelizing compilers
    Constantine Polychronopoulos, University of Illinois
o Mechanisms for exploiting instruction-level parallelism
    Yale Patt, University of Michigan
o Instruction-level parallelizing compilers
    Alexandru Nicolau, University of California, Irvine
o Multitheaded Computer Architecture
    Jack B. Dennis, MIT. Laboratory for Computer Science

                                                CONFERENCE AT A GLANCE
                                                    MONDAY, JUNE 26
  8:00 - 12:00 Tutorials 1 and 2
  1:00 - 5:00 Tutorials 3 and 4
T1 = Front-end parallelizing compilers, Constantine Polychronopoulos
T2 = Mechanisms for exploiting instruction-level parallelism, Yale Patt
T3 = Instruction-level parallelizing compilers, Alexandru Nicolau
T4 = Multitheaded Computer Architecture, Jack B. Dennis
                                                    TUESDAY, JUNE 27
  9:00 - 9:30 Opening Remarks
  9:30 - 10:30 Invited Talk Yale Patt, University of Michigan
11:00 - 12:30 Session 1 Compiling for IL Parallelism
  1:30 - 3:30 Session 2 Multithreading I
  4:00 - 5:30 Session 3 Short papers
  5:30 - 7:30 Reception Poster Presentations/Reception Room 1234
                                                    WEDNESDAY, JUNE 28
  9:00 - 10:00 Invited Talk Jim Smith, University of Wisconsin
10:30 - 12:30 Session 4 Cache Coherence/ILP Architecture
  1:30 - 3:00 Session 5 Multithreading II
  3:30 - 5:00 Session 6 Functional Programming/Single Assignment
  5:30 - 6:30 Panel NOW: is there No Other Way
  7:30 - 9:00 Banquet
                                                    THURSDAY, JUNE 29
  9:00 - 10:00 Invited Talk David Padua, University of Illinois
10:30 - 12:30 Session 7 Analysis/Scheduling
  1:30 - 3:00 Session 8 Performance Evaluation
  3:30 - 5:30 Session 9 Data Parallelism
                              FRIDAY, JUNE 30 Optional Group Excursions

                                        PACT'95 PRELIMINARY PROGRAM
                                                    MONDAY, JUNE 26

o Front-end parallelizing compilers
    Constantine Polychronopoulos, University of Illinois
o Mechanisms for exploiting instruction-level parallelism
    Yale Patt, University of Michigan
o Instruction-level parallelizing compilers
    Alexandru Nicolau, University of California, Irvine
o Multitheaded Computer Architecture
    Jack B. Dennis, M.I.T. Laboratory for Computer Science

                                                  TUESDAY, JUNE 27

INVITED TALK 1 (9:30-10:30)
    Instruction-level parallelism, Yale Patt, University of Michigan

SESSION 1 (11:00-12:30) Compiling for ILP
    Chair: Yale Patt

o Register Allocation Sensitive Region Scheduling,
    Cindy Norris and Lori L. Pollock, University of Delaware

o CRAIG: A Practical Framework for Combining Instruction Scheduling
    and Register Assignment, Thomas S. Brasier, Microware Systems
    Corporation, Philip H. Sweany, Michigan Technological University,
    Steven J. Beaty, Cray Computer Corporation, and Steve Carr, Michigan
    Technological University.

o Compiler Techniques for Data Fetching on PowerPC,
    D. Bernstein, D. Cohen, and A. Freund, IBM Haifa Research Laboratory

SESSION 2 (1:30-3:30) Multithreading
    Chair: Makoto Amamiya

o Multithreading with the EM-4 Distributed-Memory Multiprocessor,
    Andrew Sohn, New Jersey Institute of Technology, Chinhyun Kim,
    Louisiana Tech, Mitsuhisa Sato, Electrotechnical Laboratory, Japan

o Ordered Multithreading: A Novel Technique for Exploiting
    Thread-Level Parallelism, M. Motomura, NEC Corporation, T. Inoue,
    System ULSI Research Laboratory, S. Torii, and A. Konagaya, C&C
    Research Laboratories, Japan.

o Increasing Superscalar Performance Through Multistreaming, Wayne
    Yamamoto, National Semiconductor Corp. and UC Santa Barbara,
    and Mario Nemirovsky, UC Santa Barbara

o A Study of the EARTH Multiprocessor,
    H.H.J. Hum, O. Maquelin, K.B. Theobald, X. Tian, X. Tang, G.R. Gao,
    P. Cupryk, N. Elmasri, L.J. Hendren, A. Jimenez, S. Krishnan, A. Marquez,
    S. Merali, S. Nemawarkar, P. Panangaden, X. Xue, and Y. Zhu,
    McGill University and Concordia University, Canada.

SESSION 3 (4:00-5:30) Short Papers
    Chair: Greg Egan

o The meeting graph: a New Model for Loop Cyclic Register Allocation,
    Christine Eisenbeis, Sylvain Lelait and Bruno Marmol, INRIA, France.

o Transformation of Functional Specifications of Finite Difference Methods
    to Parallel Distributed Codes, Kanad Roy and Carl McCrosky,
    University of Saskatchewan, Canada.

o Using Compilers for Heterogeneous System Design,
    Rainer Leupers and Peter Marwedel, University of Dortmund, Germany.

o Decomposed Software Pipelining with Reduced Register Requirement,
    J. Wang, A. Krall, and M.A. Ertl, Technische Universitat Wien, Austria.

o Self-Parallelization of Sequential Object Codes,
    R.N. Rechtschaffen and K. Ekanadham, IBM T.J. Watson Research Center.

o A Loop Parallelization Technique for Linear Dependence Vector, T. Kitasuka,
    K. Joe, D. Schouten*, A. Fukuda, and K. Arak, Nara Institute of Science
    and Technology, * University of Illinois.

o Allocating Registers in Multiple Instruction-Issuing Processors, C. Eisenbeis,
    INRIA, France, F. Gasperoni, Telecom Paris, France, and U. Schwiegelshohn,
    University of Dortmundm, Germany.

o Increasing Cache Bandwidth Using Multi-Port Caches for Exploiting ILP
    in Non-numerical Code, Soo-Mook Moon, Seoul National University, Korea.

o Automatic Generation of Loop Scheduling for VLIW, C. Barrado, J. Labarta,
    E. Ayguade, and M. Valero, Universidat Politechnica de Catalunya, Spain.

o A Proposal of Self-Cleanup Cache, S-I Mori, M. Goshima, H. Nakashima
    and S. Tomita, Kyoto University

o Performance Impact of Architectural Features during Binary to Binary
    Translation, B.H. Cogswell Carnegie Mellon University, and Z. Segall,
    University of Oregon.

o Hyperscalar Processor Architecture - Principle of Operations and
    Preliminary Performance Evaluation, K. Murakami, H. Miyajima, Y. Saitoh,
    and T. Hironaka, Kyushu University, Japan.

o From Functional Equations to Occam Programs: Systolizing Compilation,
    Elena Trichina, University of Joensuu, Finland.

o Solving ODEs with Extrapolation Methods on Optimal Systolic Arrays,
    O. Brudaru and C.H. Skiadas, Technical University of Crete, Greece.

POSTER PRESENTATIONS/Reception (5:30-7:30)

                                                      WEDNESDAY, JUNE 28

INVITED TALK 2 (9:00-10:00)
    New Paradigms for ILP, Jim Smith, University of Wisconsin

SESSION 4 (10:30-12:30) Cache Coherence/ILP Architecture
    Chair: Mario Nemirovsky

o A Compiler Algorithm that Reduces Read Latency in Ownership-Based Cache
    Coherence Protocols, Jonas Skeppstedt and Per Stenstrom, Lund University

o Direct-Mapped Versus Set-Associative Pipelined Caches, Nathalie Drach,
    Universite de Paris XI, Andre Seznec, INRIA/IRISA, and Daniel Windheiser,
    SEH/ETCA, France.

o The Influence of Branch Prediction Table Interference on Branch Prediction
    Scheme Performance, Adam R. Talcott (1), Mario Nemirovsky (1 & 2),
    and Roger C. Wood (1), (1) UC Santa Barbara, (2) National Semiconductor Corp.

o Using Predicated Execution to Improve the Performance of a
    Dynamically-Scheduled Machine With Speculative Execution, Po-Yung Chang,
    Eric Hao, Yale Patt, University of Michigan, and Pohua Chang, Intel.

SESSION 5 (1:30-3:00) Multithreading
    Chair: Shuichi Sakai

o Single-Program Speculative Multithreading (SPSM) Architecture:
    Compiler-assisted Fine-Grained Multithreading, P.K. Dubey, Kevin
    O'Brien, Kathryn O'Brien, and C. Barton, IBM T. J. Watson Research Center

o Analysis of Communications and Overhead Reduction in Multithreading Execution,
    L. Roh and W.A. Najjar, Colorado State University

o Control of Parallelism in Multithreading Code, B. Shankar, L. Roh,
    W. Bohm, and W. Najjar, Colorado State University

SESSION 6 (3:30-5:00) Functional Programming/Single Assignment
    Chair: Wim Bohm

o Effects of Data Bundling in Non-Strict Data Structures, Eun Ha Rho,
    Sang Yong Han, Seoul National University, Heung Hwan Kim, Seowon
    University, and Dae Joon Hwang, SungKyunKwan University, Korea

o A Practical Approach to Single Assignment Code, Patricia Pineo,
    Allegheny College, PA, and Mary Lou Soffa, University of Pittsburgh

PANNEL (5:30-6:30) NOW: is there No Other Way

BANQUET (7:30 - 9:00)

                                                              THURSDAY, JUNE 29

INVITED TALK 3 (9:00-10:00)
    Trends in Compiler Technology for Parallel Computers
    David Padua, University of Illinois

SESSION 7 (10:30-12:30) Analysis/Scheduling
    Chair: Michel Cosnard

o A Simple Algorithm for the Generation of Efficient Loop Structures,
    M. Cosnard and M. Loi, ENS Lyon, France.

o Data Flow Analysis of Parallel Programs,
    Jurgen Vollmer, Universitat Karlsruhe, Germany.

o Scheduling Optimization Through Iterative Refinement, Mayez Al-Mouhamed and
    Adel Masarani, King Fahd University, Saudi Arabia.

o Mappings for Communication Minimization Using Distribution and Alignment,
    Catherine Mongenet, Universite Louis Pasteur de Strasbourg, France.

SESSION 8 (1:30-3:00) Performance Evaluation
    Chair: Gabriel Silberman

o An Analytical Model of High Performance Superscalar-Based Multiprocessors,
    David H. Albonesi and Israel Koren, University of Massachusetts

o Evaluating the Impact of Advanced Memory Systems on
    Compiler-Parallelized Codes, Evan Torrie, Chau-Wen Tseng, Stanford
    University, Margaret Martonosi, Princeton University, Mary Hall,
    California Institute of Technology.

o An Empirical Evaluation of the Convex SPP-1000 Hierarchical Shared
    Memory System, Thomas Sterling, Daniel Savarese, NASA Goddard Space Flight
    Center and University of Maryland, Phillip Merkey, and Kevin Olson,
    NASA Goddard Space Flight Center.

SESSION 9 (3:30-5:30) Data Parallelism
    Chair: Constantine Poluchronopoulos

o A Partitioning-Independent Paradigm for Nested Data Parallelism,
    Dean Engelhardt and Andrew Wendelborn, University of Adelaide, Australia.

o IPF for Real-Time Image Processing on Massively Parallel
    Architectures, Y. Robin, IRISA-INRIA, France.

o Handling Block-Cyclic Distributed Arrays in Vienna Fortran 90,
    Siegfried Benkner, University of Vienna, Austria.

o Translation of Serial Recursive Codes to Parallel SIMD Codes, Abdou
    Youssef, The George Washington Univ.

                                    FRIDAY, JUNE 30 Optional Group Excursions
                                                            END OF PACT'95

Travel agent: Ms. Despo Nicola, Tours International, Inc., 4150 Long
Beach Blvd., 3rd Floor, Long Beach, CA 90807, Tel: (310) 492-6005,
FAX: (310) 492-6288, (800) 462-8004.

Payment may be made by check, VISA, MasterCard, American Express, or
bank transfer. Checks must be made out to "PACT '95" and be drawn on a
US bank. All credit card charges will be converted to US dollars at
the rate in effect at the time the charge goes through. The deadline
for mail/fax registration is June 15, 1995. To obtain a conference
registration form, please consult the WWW page or send email to

The Limassol Sheraton is a 5-star resort hotel (highest rating
possible) on the southern beach of Cyprus. Hotel rates are 41.50 CYP
(Cyprus Pounds) single occupancy; 26.00 CYP per person double
occupancy. The approximate exchange rate is: 1 CYP = 2 US$. These
rates include all relevant taxes and will be honored 7 days prior and
7 days following the official conference dates. To guarantee a room, a
one night deposit will be required. To obtain a hotel registration
form, please consult the WWW page or send email to

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