Re: I-cache performance tuning tools

krste@ICSI.Berkeley.EDU (Krste Asanovic) writes:


>Also, any references to papers on this topic would be much appreciated.




            I-Cache Optimizations -- Classifications


                P - profile-guided
                S - static


                C - calculate conflicts (for direct-mapped cache)
                D - duplicate code to align targets
                I - inline procedures
                L - link ordering using call-frequency cliques
                M - code motion to align targets
                N - nop-padding to align targets
                R - rearrange basic blocks
                S - segregate infrequent basic blocks




            paper type C D I L M N R S
            ___________________________________________________
            Agarwal-87 P C L
            Samples-88 P R
            Hwu-89 P I L R S
            McFarling-89 P C
            Gupta-90 S D M N R
            Pettis-90 P L R S
            McFarling-91 P I
            Wu-92 P L
            Mendlson-94 P C D R




            References


            A. Agarwal, et al., "On-Chip Caches for High-Performance Proces-
            sors," Proc. 1987 Conf. on Adv. Research in VLSI, Stanford, March
            1987, pp. 1-24.


            A. Dain Samples and Paul N. Hilfinger, "Code Reorganization for
            Instruction Caches", UCB TR CSD-88-447, Oct. 1988.


            Wen-mei W. Hwu and Pohua P. Chang "Achieving High Instruction
            Cache Performance with an Optimizing Compiler", Proc. ISCA 89,
            Jerusalem, May-June 1989, pp. 242-251.


            Scott McFarling, "Program Optimization for Instruction Caches",
            Proc. ASPLOS III, Boston, April 1989, pp. 183-191.


            Rajiv Gupta and Chi-Hung Chi, "Improving Instruction Cache
            Behavior by Reducing Cache Pollution", Proc. Supercomputing 90,
            New York, November 1990, pp. 82-91.


            Karl Pettis and Robert C. Hansen, "Profile Guided Code Position-
            ing", Proc. SIGPLAN PLDI 90, White Plains, NY, June 1990, pp.
            16-27.


            Scott McFarling, "Procedure Merging with Instruction Caches",
            Proc. SIGPLAN PLDI 91, Toronto, June 1991, pp. 71-79.


            Youfeng Wu, "Ordering Functions for Improving Memory Reference
            Locality in a Shared Memory Multiprocessor System", Proc. Micro-
            25, Portland, December 1992, pp. 218-221.


            Abraham Mendlson, Shlomit S. Pinter, and Ruth Shtokhamer, "Com-
            pile Time Instruction Cache Optimizations", ACM Computer Arch.
            News, 22, 1, March 1994, pp. 44-51.




Of the above, only Rajiv Gupta considered the effect of prefetching on
i-cache optimization. I'm working with some data that shows this to be
an important effect in terms of wasted cache refill traffic (lines that
are prefetched but never used).
--
Mark Smotherman, Computer Science Dept., Clemson University, Clemson, SC
--

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