Re: On-the-fly compilation from VM code to machine code

joe@erix.ericsson.se (Joe Armstrong) writes:


>>> The VM should be a "Virtual stack machine" which has an instruction
set "no too different from a real RISC" - the compilation should be done
in real time and the resuling code should be dynamically loaded and
directly executed (Someing like the Taos operating systems described in
Byte August 1994). <<<


The problem with this is that you can't optimize RISC code "on the fly".
The efficiency of the code generated would be little better than what you
could do with an interpreter.


Having said that, using the typical RISC processor with a large register
set, you could do fairly well by just treating the register set like a
push/pop stack. Each load op "pushes" its value into the next higher
register. A monadic op "pops" the highest register and then "pushes" the
result back to the same place (NB: This doesn't make for very good RISC
code -- bad to reference the same reg twice in a single op). A diadic op
"pops" the top two regs and then "pushes" the result. The "popping" and
"pushing" done here can be mapped to static register assignment (ie, the
translator keeps a "top of stack" value that determines what regs to gen
into the next instruction) so long as you require that the stack be empty
at block entry/exit. (This restriction can be eased, but it gets messy.)


Of course you might want to worry about "stack overflow" -- saving the
oldest regs and wrapping the "top of stack" counter -- but it's unlikely
you'd need to with the typical 32 register set. Also note that the
easiest approach with float regs would be to consider them to comprise a
separate float stack (managed the same way).
[Treating the registers as a stack was the usual code generation approach
until the invention of register coloring. It still works reasonably well
considering how simple it is. -John]
--

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