Re: 'conservative' GC == 'risky' GC

boehm@parc.xerox.com (Hans Boehm) writes:
>As another example, several RISC architectures (e.g. SPARC and MIPS, I
>think) do not completely hide hardware interrupts (e.g. process
>preemptions, translation faults) from user level processes. Conventions
>dictate that user level code should not look at certain registers that may
                                                                                  ^^^^
>be affected. User code may also have to guarantee stack pointer validity
>after every instruction.


I have a copy of "The SPARC Architecture Manual", version 8. Because
register windows are not saved immediately, but may be flushed out when a
signal handler needs another window, yes, %sp must be valid at all times.
But that is the _only_ trap-related restriction I can find in that volume
on _any_ user-visible register, and you can _look_ at %sp as much as you
want. If there are other restrictions on the use of SPARC registers,
please tell me what they are.


(About the SPARC: I note that I use the 'mod' operation a lot more than
the 'div' operation, so I'm not that charmed to find that the new
{s,u}div{,cc} instructions _may_ (or may not) generate a remainder, and if
they do, they are only _recommended_ (not required) to put it in Y.
Someone at SPARC International really hates division.)
--

Return to the comp.compilers page.
Search the comp.compilers archives again.