Register Allocation and Instruction Scheduling

I am looking at the issues of Instruction Scheduling and Register
Allocation. The only literature, that I am aware of, that talk of the ills
and benefits of performing them together are listed below.


If you are aware of any others, I would be interested in knowing about
them. I would appreciate if you could eMail me at nandu@cs.clemson.edu


Of course, I would summarize them if there is sufficient interest (an
internet cliche?)




@PhDThesis{HSU:1987,
            Author = "Wei-Chung Hsu",
            Title = Register Allocation and Code Scheduling for
                                    Load\discretionary {-}{}{/}Store Architectures",
            School = "University of Wisconsin- Madsion",
            Year = 1987,
            Month = Oct,
            Note = "Computer Science Technical Report \#722"
}


@conference{GOO:HSU:1988,
            author = "Goodman, James R. and Hsu, Wei-Chung ",
            title = "Code scheduling and register allocation in large
                                      basic blocks ",
            booktitle = "Proceedings of the International Conference
                                                on Supercomputing",
            year = 1988,
            month = Jul,
            address = "St. Malo, France",
            pages = "442--452"
}


@conference{SMFJCRcgctt91,
            author = "Freudenberger, Stefan M. and Ruttenberg, John C.",
          title = "Place Ordering of Register Allocation and
                                    Instruction Scheduling",
            booktitle = "Code Generation---Concepts, Tools and Techniques",
          year = 1991,
}


@conference{BRA:EGG:HEN:1991,
            author = "${}^{\clubsuit}$Bradlee, David G. and Eggers,
                                      Susan J. and Henry, Robert R.",
            title = "Integrating Register allocation and instruction
                                      scheduling for {RISC}s",
            booktitle = ASPLOS,
            year = 1991,
            month = Apr # " 8--11",
            pages = "122--131",
            organisation = ACM,
            address = "Santa Clara, California",
            note = "Issue 26(4),1991 of SIGPLAN Notices"
}


@conference{CNLLPSupercomputing93,
            author = "${}^{\clubsuit}$Norris, C. and Pollock, L. L. ",
            title = "A Scheduler-sensitive Global Register Allocator",
            booktitle = "Proceedings of the International Conference on
                                      Supercomputing",
            year = 1993,
            month = nov,
            address = "Portland, Oregon",
            pages = "804--813"
}
--
Nandakumar Sankaran (nandu@cs.clemson.edu) (nsankar@hubcap.clemson.edu)
311-8 Old Greenville Hwy. Clemson SC 29631-1651 (803)653-7749
G34 Jordan Hall Comp. Sci. Dept. Clemson Univ. SC 29634 (803)656-6979
--

Return to the comp.compilers page.
Search the comp.compilers archives again.