Re: Instr. scheduling text suggestions

miller@sisal.llnl.gov (Patrick Miller) writes:
|> I'll be teaching a graduate compiler course this spring and I would
|> like to spend some time on instruction level scheduling. Things like
|> latency hiding, pipelining, etc...


I hold a lecture in code generation.


As an introduction I presented the architecture of modern RISC processors,
than I used chapter 9 of the dragon book, presented some code generators
(BURG, BEG) and different register allocators (Chaitin, Briggs, priority
based, Coalgulating) followed by instruction scheduling:


[GiMu86] Efficient Instruction Scheduling for a Pipelined Architecture,
Phillip B. Gibbons & Steven S. Muchnick, SIGPLAN 86 Symposium on Compiler
Construction


[Warr90] Instruction scheduling for the IBM RISC System/6000 processor,
H.S. Warren, IBM Journal of Research and Development, Vol 34, No. 1., Jan.
1990


[Lam88] Software Pipelining: An Effective Scheduling Technique for VLIW
Machines, Monica Lam, PLDI 88, SIGPLAN, June 1988


[AiNi91] A Realistic Resource-Constrained Software Pipelining Algorithm,
A, Aiken, A. Nicolau, in Advances in Languages and Compilers for Parallel
Processing, Nicolau, Gelernter, Gross and Padua (Editors), MIT Press, 1991


[GoHs88] Code Scheduling and Register Allocation in Large Basic Blocks,
James R. Goodman, Wei-Chung Hsu, International Conference on
Supercomputing, ACM 1988


[FrRu91] Phase Ordering of Register Allocation and Instruction Scheduling,
Stefan M. Freudenberger and John C. Ruttenberg, presented at Code
Generation - Concepts, Tools, Techniques, 1991


[BrEH91] Integrating Register Allocation and Instruction Scheduling for
RISCs, David G. Bradlee, Susan J. Eggers, Robert R. Henry, PLDI 91,
SIGPLAN 91


Hope this helps,
Andi


--
Andreas Krall, andi@mips.complang.tuwien.ac.at
+431 58801/4462 fax +431 5057838
Technische Univ. Wien, Inst.f. Computersprachen E185/1
Argentinierstr.8/4, A-1040 Wien Austria
--

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