List-scheduling: a RISC-driven solution?

On most architectures, the compiler has to satisfy 3 constraints when
scheduling instructions:
      -- Registers
      -- Functional Units/Issue Latency
      -- Issue Slots


On a typical RISC architecture with 32 registers, and single cycle (or
low) latency functional units, the main constraint becomes the issue slot.
Typically, an architecture can issue only one instruction per cycle. Any
scheduling algorithm that manages to schedule so that at least one
instruction is issued every cycle will do well.


An interesting phenomen:
    * Graph coloring was published in '81.
    * RISC ideas were published around '80.
    * All work on non list scheduling based scheduling algorithms ceased to be
          published around then.
    * The only work that I know of in the 80--90s era that is NOT list-schedule
          based is the stuff done by the Cydra group for their VLIW computer.


Would anyone care to agree/disagree with me? I would be _extremely_
interested to find any pointers to scheduling papers in the period 79-92
inclusive that do NOT use list scheduling.


Mayan
(moudgill@cs.cornell.edu)


P.S. Much of this information was gleaned from talking with Richard Huff.
However, I am the one responsible for the phrasing and the questions in
this article.
[Did Cydra use the Multiflow compiler or is it something else? -John]
--

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