Re: Caller allocates space for callee-save registers

pardo@cs.washington.edu writes:
>The SPARC architecture does not define user-level traps. Window
>management (except for executing `save' and `restore' instructions)
>requires kernel-mode access. I believe that one better design would have
>an array of registers and a current base pointer similar to the current
>SPARC but would put management entirely in user space, have user-level
>traps for over- and underflow and dedicate a global for kernel use and a
>global for window handler use...


You've described, essentially, the AMD 29000. Nice machine; too bad it is
being marketed primarily for the embedded-control market.


Bonuses on the 29000 are that (a) window size is your choice, anywhere
between 2 and 126 registers, (b) there are 64 global registers as well,
and (c) you can address all of them without bank-switching if you just
plain need a lot of registers. The traps don't go direct to user space,
but the kernel "trampoline" overhead to punt them back is very small, a
dozen cycles or so.


And if you really insist, you can run it like a SPARC, with fixed windows
and the kernel doing all the work. (However, no, it is *not* the same
instruction set.)


The price you pay, incidentally, for all those registers being easily
addressable, is no offsets in memory addressing. The usual RISC
addressing modes are register, short immediate, and memory at (register +
short offset). On the 29000, it's register, short immediate, and memory
at (register). You get no free address arithmetic, so the penalty for not
exploiting the registers well is higher.
--
Henry Spencer @ U of Toronto Zoology, henry@zoo.toronto.edu utzoo!henry
--

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