Summary to post: YACC-able grammars for VHDL or Verilog

Here is a summary of the responses I got to a request for a
Verilog or VHDL grammar:
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both VHDL and Verilog are yacc'able. [..]
Yaccing VHDL is harder than Yaccing Verilog, again quite obviously.
[There are a] lot of semantic rules that interact with the lexer to make
it happen for VHDL. yacc for Verilog is fairly straight forward.


i think a yacc parser should be available from Open Verilog International
(OVI). i am not sure about the toolkits available, but i can certainly find
out for you.


cheers,
--
bang: uunet!cadence!bammi jwahar r. bammi
domain: bammi@cadence.com
GEnie: J.Bammi
CIS: 71515,155




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This is probably not very useful to you, but Vantage has one,
more or less. They use an attribute grammar based system (Linguist).
If you're interested in Linguist, contact Rodney Farrow of
Declarative Systems at 415-321-2613 (Palo Alto).


David Chase (David.Chase@Eng.Sun.COM)
Sun


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The back of the manual (and both Verilog book) contain the BNF grammer of
the language. However, there is a great deal of work that need to be done
to make the grammer YACC-able.


[..]


-Elliot Mednick (elliot@unixland.natick.ma.us)


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There is one that was developed by folks at the Univ of Cincinnatti, and
is probably ftp-able from there. If you don't find it, let me know and
I'll look.


Unfortunately, I dont get to read my mail here very often so there may be
a delay in getting back to you. Try also FTPing from bears.usc.edu (or
some similarly named machine), they have a lot of vhdl stuff and are bound
to have it.


In case you havent tried already, comp.lang.vhdl will
probably have a quick answer for you.


- VV (szebra!Saigon.COM!bbs@sonyusa.Sony.COM)
-------


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[The following refers to VHDL only]


Whether it is YACC-able or not depends on how much you expect YACC to do
for you. If I remember correctly VHDL shares a lot of its grammatical
structure with Ada. This means you can't for example tell the difference
between an array access and a function call purely from the syntax. To
differentiate you need to do one of a number of different things, the most
common being to look in the symbol table to see what a particular
identifier is currently bound to. However as VHDL allows overloading of
names, it isn't always easy.


So in summary, yes a YACC parser can be constructed for VHDL, but you'll
have to add lots of "semantic" functions to restrict your parser to the
grammar given in the LRM.




Stephen J. Bevan bevan@cs.man.ac.uk


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The University of Cincinnati does a lot with VHDL. I'm writing a
transtalor from VHDL to a data flow graph format, and use a YACC source
from that University. It's not easy to device a decent YACC file for VHDL,
but it is possible.




pooh@viper.es.ele.tue.nl


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Joe,


Try anonymous ftp file /vhdl/tools/uc_vhdlgrammar from uceng.uc.edu .


--
  Toan Tran
toan@cdc.hp.com


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[Mailed to comp.compilers but included here for completeness]




The Verilog Hardware Description Language
by D.E.Thomas (CMU) and P.Moorby (Cadence)
Kluwer Academic Publishers 1991


contains a formal description of the language in Appendix F which looks
like it would yield a yaccable grammar file.


Cheers
Hamish (htf@castle.ed.ac.uk)


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joe,


last year, we had a ftp'able vhdl grammar. check on ``uceng.uc.edu''.
note, i am not the contact point on this grammar. you should check with
hal carter (hcarter@thor.ece.uc.edu (513) 556-4781).


Philip A. Wilsey phil.wilsey@uc.edu


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The VHDL grammar in the IEEE-LRM is LL(1), so it certainly is YACC-able
(in fact, one company, Model Technology Inc, based in Oregon, based their
VHDL "compiler" on yacc/bison).


As for Verilog, it probably is yacc-able, with a few hacks. Gateway
Design Automation, the originators of the language, in fact, hand- crafted
their compiler for the language (for speed reasons, so I am told).


(I saw the response referencing the "Verilog book". Is this book any good
??)


Karl W. Pfalzer (dolphin!sunami!pfalzer@asuvax.eas.asu.edu)
(602) 752-6255


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You can get verilog grammar from verilog manuals available from Cadence.
This grammar is indeed yaccable.


I am trying to build a graph compiler which takes in hardware descriptions
in verilog and generates a control data flow graph. This is going to be
the front end for a high level synthesis system.




Right now I have written Lex and Yacc description for verilog and built in
some action into parser which reads in a ascii file having verilog
description of a module with a bunch of equations and generate a graph,
nodes of which are adders or multipliers. The description of the graph
gives the immediate successors of each of the node. This data can be used
for a next stage scheduler and allocator programmes of our high level
synthesis system.


I am mailing you files conv.l (lex description), conv.y (yacc
description), makefile, infile(input file) and outfile(output file). All
these files are concatenated . You can separate these by looking at the
comments. If you prefer an archived directory let me know, and I will
mail you that.




Though I have written yacc description for all of verilog, actions are
written only for a some of the statements for test purposes. The project
needs lot more work and refinement. I hope this will be of some help to
you.


Regards
Aditya Krishna
ska@swamp.cacs.usl.edu
(318) 237-4850


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Joe Varghese | varghese@mentor.com OR joe_varghese@mentorg.com
Mentor Graphics Corporation | (503) 685 7000 x2227
8005 SW Boeckman Road |
Wilsonville, OR 97070 |
--

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